Lines Matching +full:phy +full:- +full:ref +full:- +full:clk

1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR803x PHY
10   - Andrew Lunn <andrew@lunn.ch>
11   - Florian Fainelli <f.fainelli@gmail.com>
12   - Heiner Kallweit <hkallweit1@gmail.com>
18   - $ref: ethernet-phy.yaml#
21   qca,clk-out-frequency:
23     $ref: /schemas/types.yaml#/definitions/uint32
26   qca,clk-out-strength:
28     $ref: /schemas/types.yaml#/definitions/uint32
31   qca,disable-smarteee:
35   qca,keep-pll-enabled:
43   qca,smarteee-tw-us-100m:
45     $ref: /schemas/types.yaml#/definitions/uint32
49   qca,smarteee-tw-us-1g:
51     $ref: /schemas/types.yaml#/definitions/uint32
55   vddio-supply:
59       The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can
60       either connect this to the vddio-regulator (1.5V / 1.8V) or the
61       vddh-regulator (2.5V).
65   vddio-regulator:
69     $ref: /schemas/regulator/regulator.yaml
71   vddh-regulator:
74       Dummy subnode to model the external connection of the PHY VDDH
76     $ref: /schemas/regulator/regulator.yaml
81   - |
82     #include <dt-bindings/net/qca-ar803x.h>
85         #address-cells = <1>;
86         #size-cells = <0>;
88         phy-mode = "rgmii-id";
90         ethernet-phy@0 {
93             qca,clk-out-frequency = <125000000>;
94             qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
96             vddio-supply = <&vddio>;
98             vddio: vddio-regulator {
99                 regulator-min-microvolt = <1800000>;
100                 regulator-max-microvolt = <1800000>;
104   - |
105     #include <dt-bindings/net/qca-ar803x.h>
108         #address-cells = <1>;
109         #size-cells = <0>;
111         phy-mode = "rgmii-id";
113         ethernet-phy@0 {
116             qca,clk-out-frequency = <50000000>;
117             qca,keep-pll-enabled;
119             vddio-supply = <&vddh>;
121             vddh: vddh-regulator {