Lines Matching +full:sparx5 +full:- +full:sgpio
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 Ethernet switch controller
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The SparX-5 Enterprise Ethernet switch family provides a rich set of
15 Enterprise switching features such as advanced TCAM-based VLAN and
17 security through TCAM-based frame processing using versatile content
25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
28 The SparX-5 switch family targets managed Layer 2 and Layer 3
34 pattern: "^switch@[0-9a-f]+$"
37 const: microchip,sparx5-switch
41 - description: cpu target
42 - description: devices target
43 - description: general control block target
45 reg-names:
47 - const: cpu
48 - const: devices
49 - const: gcb
54 - description: register based extraction
55 - description: frame dma based extraction
57 interrupt-names:
60 - const: xtr
61 - const: fdma
65 - description: Reset controller used for switch core reset (soft reset)
67 reset-names:
69 - const: switch
71 mac-address: true
73 ethernet-ports:
76 "^port@[0-9a-f]+$":
80 '#address-cells':
82 '#size-cells':
94 phy-mode:
104 phy-handle:
117 microchip,sd-sgpio:
119 Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs
127 - reg
128 - phys
129 - phy-mode
130 - microchip,bandwidth
133 - required:
134 - phy-handle
135 - required:
136 - sfp
137 - managed
140 - compatible
141 - reg
142 - reg-names
143 - interrupts
144 - interrupt-names
145 - resets
146 - reset-names
147 - ethernet-ports
152 - |
153 #include <dt-bindings/interrupt-controller/arm-gic.h>
155 compatible = "microchip,sparx5-switch";
159 reg-names = "cpu", "devices", "gcb";
161 interrupt-names = "xtr";
163 reset-names = "switch";
164 ethernet-ports {
165 #address-cells = <1>;
166 #size-cells = <0>;
172 phy-handle = <&phy0>;
173 phy-mode = "qsgmii";
181 phy-mode = "10gbase-r";
183 managed = "in-band-status";
184 microchip,sd-sgpio = <365>;
190 phy-mode = "10gbase-r";
192 managed = "in-band-status";
193 microchip,sd-sgpio = <369>;
199 phy-mode = "10gbase-r";
201 managed = "in-band-status";
202 microchip,sd-sgpio = <373>;
208 phy-mode = "10gbase-r";
210 managed = "in-band-status";
211 microchip,sd-sgpio = <377>;
218 phy-handle = <&phy64>;
219 phy-mode = "sgmii";
220 mac-address = [ 00 00 00 01 02 03 ];