Lines Matching +full:imx27 +full:- +full:clock
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Joakim Zhang <qiangqing.zhang@nxp.com>
13 - $ref: ethernet-controller.yaml#
18 - enum:
19 - fsl,imx25-fec
20 - fsl,imx27-fec
21 - fsl,imx28-fec
22 - fsl,imx6q-fec
23 - fsl,mvf600-fec
24 - items:
25 - enum:
26 - fsl,imx53-fec
27 - fsl,imx6sl-fec
28 - const: fsl,imx25-fec
29 - items:
30 - enum:
31 - fsl,imx35-fec
32 - fsl,imx51-fec
33 - const: fsl,imx27-fec
34 - items:
35 - enum:
36 - fsl,imx6ul-fec
37 - fsl,imx6sx-fec
38 - const: fsl,imx6q-fec
39 - items:
40 - enum:
41 - fsl,imx7d-fec
42 - const: fsl,imx6sx-fec
43 - items:
44 - const: fsl,imx8mq-fec
45 - const: fsl,imx6sx-fec
46 - items:
47 - enum:
48 - fsl,imx8mm-fec
49 - fsl,imx8mn-fec
50 - fsl,imx8mp-fec
51 - const: fsl,imx8mq-fec
52 - const: fsl,imx6sx-fec
53 - items:
54 - const: fsl,imx8qm-fec
55 - const: fsl,imx6sx-fec
56 - items:
57 - enum:
58 - fsl,imx8qxp-fec
59 - const: fsl,imx8qm-fec
60 - const: fsl,imx6sx-fec
69 interrupt-names:
71 - items:
72 - const: int0
73 - items:
74 - const: int0
75 - const: pps
76 - items:
77 - const: int0
78 - const: int1
79 - const: int2
80 - items:
81 - const: int0
82 - const: int1
83 - const: int2
84 - const: pps
91 The "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock.
92 The "ptp"(option), for IEEE1588 timer clock that requires the clock.
93 The "enet_clk_ref"(option), for MAC transmit/receiver reference clock like
94 RGMII TXC clock or RMII reference clock. It depends on board design,
95 the clock is required if RGMII TXC and RMII reference clock source from
97 The "enet_out"(option), output clock for external device, like supply clock
98 for PHY. The clock is required if PHY clock source from SOC.
99 The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz.
100 The clock is required if SoC RGMII enable clock delay.
102 clock-names:
107 - ipg
108 - ahb
109 - ptp
110 - enet_clk_ref
111 - enet_out
112 - enet_2x_txclk
114 phy-mode: true
116 phy-handle: true
118 fixed-link: true
120 local-mac-address: true
122 mac-address: true
124 tx-internal-delay-ps:
127 rx-internal-delay-ps:
130 phy-supply:
134 fsl,num-tx-queues:
137 The property is valid for enet-avb IP, which supports hw multi queues.
141 fsl,num-rx-queues:
144 The property is valid for enet-avb IP, which supports hw multi queues.
148 fsl,magic-packet:
153 fsl,err006687-workaround-present:
159 fsl,stop-mode:
160 $ref: /schemas/types.yaml#/definitions/phandle-array
173 # To avoid these, create a phy node according to ethernet-phy.yaml in the same
174 # directory, and point the FEC's "phy-handle" property to it. Then use
175 # the phy's reset binding, again described by ethernet-phy.yaml.
177 phy-reset-gpios:
182 phy-reset-duration:
186 "phy-reset-gpios" is available. Missing the property will have the
190 phy-reset-active-high:
194 "phy-reset-gpios" property is reversed (H=reset state, L=operation state).
196 phy-reset-post-delay:
199 Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay
200 milliseconds will be observed after the phy-reset-gpios has been toggled.
205 - compatible
206 - reg
207 - interrupts
216 - |
218 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
221 phy-mode = "mii";
222 phy-reset-gpios = <&gpio2 14 0>;
223 phy-supply = <®_fec_supply>;
227 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
230 phy-mode = "mii";
231 phy-reset-gpios = <&gpio2 14 0>;
232 phy-supply = <®_fec_supply>;
233 phy-handle = <ðphy0>;
236 #address-cells = <1>;
237 #size-cells = <0>;
239 ethphy0: ethernet-phy@0 {
240 compatible = "ethernet-phy-ieee802.3-c22";