Lines Matching +full:rb +full:- +full:gpios

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Miquel Raynal <miquel.raynal@bootlin.com>
11   - Richard Weinberger <richard@nod.at>
24   The interpretation of these parameters is implementation-defined, so
31     pattern: "^nand-controller(@.*)?"
33   "#address-cells":
36   "#size-cells":
41   cs-gpios:
45       Array of chip-select available to the controller. The first
46       entries are a 1:1 mapping of the available chip-select on the
48       chip-select as needed may follow and should be phandles of GPIO
53   "^nand@[a-f0-9]$":
60       nand-ecc-engine:
62           - $ref: /schemas/types.yaml#/definitions/phandle
68           2/ The ECC engine is part of the NAND part (on-die), in this
73       nand-use-soft-ecc-engine:
77       nand-no-ecc-engine:
81       nand-ecc-placement:
83           - $ref: /schemas/types.yaml#/definitions/string
84           - enum: [ oob, interleaved ]
91       nand-ecc-algo:
97       nand-bus-width:
104       nand-on-flash-bbt:
110           it as the device ages. Otherwise, the out-of-band area of a
115       nand-ecc-strength:
121       nand-ecc-step-size:
127       nand-ecc-maximize:
135           only the in-band area is used by the upper layers, and you
138       nand-is-boot-medium:
145       nand-rb:
146         $ref: /schemas/types.yaml#/definitions/uint32-array
150       rb-gpios:
157       secure-regions:
158         $ref: /schemas/types.yaml#/definitions/uint64-matrix
165       - reg
168   - "#address-cells"
169   - "#size-cells"
174   - |
175     nand-controller {
176       #address-cells = <1>;
177       #size-cells = <0>;
178       cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */
184         nand-use-soft-ecc-engine;
185         nand-ecc-algo = "bch";