Lines Matching full:nand
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
31 pattern: "^nand-controller(@.*)?"
47 NAND controller (even if they are not used). As many additional
49 lines. 'reg' entries of the NAND chip subnodes become indexes of
53 "^nand@[a-f0-9]$":
60 nand-ecc-engine:
66 1/ The ECC engine is part of the NAND controller, in this
68 2/ The ECC engine is part of the NAND part (on-die), in this
73 nand-use-soft-ecc-engine:
77 nand-no-ecc-engine:
81 nand-ecc-placement:
91 nand-ecc-algo:
97 nand-bus-width:
99 Bus width to the NAND chip
104 nand-on-flash-bbt:
115 nand-ecc-strength:
121 nand-ecc-step-size:
127 nand-ecc-maximize:
136 want to make your NAND as reliable as possible.
138 nand-is-boot-medium:
141 Whether or not the NAND chip is a boot medium. Drivers might
145 nand-rb:
154 Ready/Busy pins. Active state refers to the NAND ready state and
160 Regions in the NAND chip which are protected using a secure element
175 nand-controller {
182 nand@0 {
184 nand-use-soft-ecc-engine;
185 nand-ecc-algo = "bch";
190 nand@1 {