Lines Matching full:ecc
19 The ECC strength and ECC step size properties define the user
21 they request the ECC engine to correct {strength} bit errors per
60 nand-ecc-engine:
64 A phandle on the hardware ECC engine if any. There are
66 1/ The ECC engine is part of the NAND controller, in this
68 2/ The ECC engine is part of the NAND part (on-die), in this
70 3/ The ECC engine is external, in this case the phandle should
71 reference the specific ECC engine node.
73 nand-use-soft-ecc-engine:
75 description: Use a software ECC engine.
77 nand-no-ecc-engine:
79 description: Do not use any ECC correction.
81 nand-ecc-placement:
86 Location of the ECC bytes. This location is unknown by default
87 but can be explicitly set to "oob", if all ECC bytes are
88 known to be stored in the OOB area, or "interleaved" if ECC
91 nand-ecc-algo:
93 Desired ECC algorithm.
115 nand-ecc-strength:
117 Maximum number of bits that can be corrected per ECC step.
121 nand-ecc-step-size:
123 Number of data bytes covered by a single ECC step.
127 nand-ecc-maximize:
130 Whether or not the ECC strength should be maximized. The
131 maximum ECC strength is both controller and chip
132 dependent. The ECC engine has to select the ECC config
142 use this information to select ECC algorithms supported by
184 nand-use-soft-ecc-engine;
185 nand-ecc-algo = "bch";