Lines Matching +full:gcc +full:- +full:sc7280
1 * Qualcomm SDHCI controller (sdhci-msm)
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain a SoC-specific string and a IP version string:
9 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
10 "qcom,sdhci-msm-v5" for sdcc version 5.0
13 string is added to support this change - "qcom,sdhci-msm-v5".
15 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
16 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
17 "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
18 "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
19 "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"
20 "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"
21 "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
22 "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
23 "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"
24 "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
25 "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"
27 have the string "qcom,sdhci-msm-v4" without the SoC compatible string
30 - reg: Base address and length of the register in the following order:
31 - Host controller register map (required)
32 - SD Core register map (required for controllers earlier than msm-v5)
33 - CQE register map (Optional, CQE support is present on SDHC instance meant
35 - Inline Crypto Engine register map (optional)
36 - reg-names: When CQE register map is supplied, below reg-names are required
37 - "hc" for Host controller register map
38 - "core" for SD core register map
39 - "cqhci" for CQE register map
40 - "ice" for Inline Crypto Engine register map (optional)
41 - interrupts: Should contain an interrupt-specifiers for the interrupts:
42 - Host controller interrupt (required)
43 - pinctrl-names: Should contain only one value - "default".
44 - pinctrl-0: Should specify pin control groups used for this controller.
45 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
46 - clock-names: Should contain the following:
47 "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
48 "core" - SDC MMC clock (MCLK) (required)
49 "bus" - SDCC bus voter clock (optional)
50 "xo" - TCXO clock (optional)
51 "cal" - reference clock for RCLK delay calibration (optional)
52 "sleep" - sleep clock for RCLK delay calibration (optional)
53 "ice" - clock for Inline Crypto Engine (optional)
55 - qcom,ddr-config: Certain chipsets and platforms require particular settings
59 - qcom,dll-config: Chipset and Platform specific value. Use this field to
64 - interconnects: Pairs of phandles and interconnect provider specifier
68 - interconnect-names: For sdhc, we have two main paths.
72 is "sdhc-ddr" and for config interconnect path it is
73 "cpu-sdhc".
80 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
83 bus-width = <8>;
84 non-removable;
86 vmmc-supply = <&pm8941_l20>;
87 vqmmc-supply = <&pm8941_s3>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
92 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
93 clock-names = "core", "iface";
96 interconnect-names = "sdhc-ddr","cpu-sdhc";
98 qcom,dll-config = <0x000f642c>;
99 qcom,ddr-config = <0x80040868>;
103 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
106 bus-width = <4>;
107 cd-gpios = <&msmgpio 62 0x1>;
109 vmmc-supply = <&pm8941_l21>;
110 vqmmc-supply = <&pm8941_l13>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
115 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
116 clock-names = "core", "iface";
118 qcom,dll-config = <0x0007642c>;
119 qcom,ddr-config = <0x80040868>;