Lines Matching +full:hs200 +full:- +full:cmd +full:- +full:int +full:- +full:delay
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
14 - $ref: mmc-controller.yaml#
19 - enum:
20 - mediatek,mt2701-mmc
21 - mediatek,mt2712-mmc
22 - mediatek,mt6779-mmc
23 - mediatek,mt7620-mmc
24 - mediatek,mt7622-mmc
25 - mediatek,mt8135-mmc
26 - mediatek,mt8173-mmc
27 - mediatek,mt8183-mmc
28 - mediatek,mt8516-mmc
29 - items:
30 - const: mediatek,mt7623-mmc
31 - const: mediatek,mt2701-mmc
32 - items:
33 - const: mediatek,mt8192-mmc
34 - const: mediatek,mt8183-mmc
35 - items:
36 - const: mediatek,mt8195-mmc
37 - const: mediatek,mt8183-mmc
44 - description: source clock (required).
45 - description: HCLK which used for host (required).
46 - description: independent source clock gate (required for MT2712).
47 - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
48 - description: msdc subsys clock gate (required for MT8192).
49 - description: peripheral bus clock gate (required for MT8192).
50 - description: AXI bus clock gate (required for MT8192).
51 - description: AHB bus clock gate (required for MT8192).
53 clock-names:
56 - const: source
57 - const: hclk
58 - const: source_cg
59 - const: bus_clk
60 - const: sys_cg
61 - const: pclk_cg
62 - const: axi_cg
63 - const: ahb_cg
65 pinctrl-names:
67 - const: default
68 - const: state_uhs
70 pinctrl-0:
75 pinctrl-1:
80 assigned-clocks:
85 assigned-clock-parents:
90 hs400-ds-delay:
93 HS400 DS delay setting.
97 mediatek,hs200-cmd-int-delay:
100 HS200 command internal delay setting.
106 mediatek,hs400-cmd-int-delay:
109 HS400 command internal delay setting.
115 mediatek,hs400-cmd-resp-sel-rising:
122 mediatek,latch-ck:
125 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
128 applied to compatible "mediatek,mt2701-mmc".
135 reset-names:
139 - compatible
140 - reg
141 - interrupts
142 - clocks
143 - clock-names
144 - pinctrl-names
145 - pinctrl-0
146 - pinctrl-1
147 - vmmc-supply
148 - vqmmc-supply
153 - |
154 #include <dt-bindings/interrupt-controller/irq.h>
155 #include <dt-bindings/interrupt-controller/arm-gic.h>
156 #include <dt-bindings/clock/mt8173-clk.h>
158 compatible = "mediatek,mt8173-mmc";
161 vmmc-supply = <&mt6397_vemc_3v3_reg>;
162 vqmmc-supply = <&mt6397_vio18_reg>;
165 clock-names = "source", "hclk";
166 pinctrl-names = "default", "state_uhs";
167 pinctrl-0 = <&mmc0_pins_default>;
168 pinctrl-1 = <&mmc0_pins_uhs>;
169 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
170 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
171 hs400-ds-delay = <0x14015>;
172 mediatek,hs200-cmd-int-delay = <26>;
173 mediatek,hs400-cmd-int-delay = <14>;
174 mediatek,hs400-cmd-resp-sel-rising;