Lines Matching +full:mode +full:- +full:flag
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
38 $ref: /schemas/types.yaml#/definitions/flag
42 cd-gpios:
47 non-removable:
48 $ref: /schemas/types.yaml#/definitions/flag
50 Non-removable slot (like eMMC); assume always present.
56 # low." Therefore, using the "cd-inverted" property means, that the
58 # inserted. Similar logic applies to the "wp-inverted" property.
61 # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
63 # using *-inverted properties. GPIO polarity can also be specified
64 # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the
67 # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
68 # respective *-inverted property property results in a
69 # double-inversion and actually means the "normal" line polarity is
71 wp-inverted:
72 $ref: /schemas/types.yaml#/definitions/flag
76 cd-inverted:
77 $ref: /schemas/types.yaml#/definitions/flag
83 bus-width:
90 max-frequency:
97 disable-wp:
98 $ref: /schemas/types.yaml#/definitions/flag
100 When set, no physical write-protect line is present. This
102 dedicated write-protect detection logic. If a GPIO is always used
103 for the write-protect detection logic, it is sufficient to not
104 specify the wp-gpios property in the absence of a write-protect
107 wp-gpios:
110 GPIO to use for the write-protect detection.
112 cd-debounce-delay-ms:
117 no-1-8-v:
118 $ref: /schemas/types.yaml#/definitions/flag
123 cap-sd-highspeed:
124 $ref: /schemas/types.yaml#/definitions/flag
126 SD high-speed timing is supported.
128 cap-mmc-highspeed:
129 $ref: /schemas/types.yaml#/definitions/flag
131 MMC high-speed timing is supported.
133 sd-uhs-sdr12:
134 $ref: /schemas/types.yaml#/definitions/flag
138 sd-uhs-sdr25:
139 $ref: /schemas/types.yaml#/definitions/flag
143 sd-uhs-sdr50:
144 $ref: /schemas/types.yaml#/definitions/flag
148 sd-uhs-sdr104:
149 $ref: /schemas/types.yaml#/definitions/flag
153 sd-uhs-ddr50:
154 $ref: /schemas/types.yaml#/definitions/flag
158 cap-power-off-card:
159 $ref: /schemas/types.yaml#/definitions/flag
163 cap-mmc-hw-reset:
164 $ref: /schemas/types.yaml#/definitions/flag
168 cap-sdio-irq:
169 $ref: /schemas/types.yaml#/definitions/flag
173 full-pwr-cycle:
174 $ref: /schemas/types.yaml#/definitions/flag
178 full-pwr-cycle-in-suspend:
179 $ref: /schemas/types.yaml#/definitions/flag
183 mmc-ddr-1_2v:
184 $ref: /schemas/types.yaml#/definitions/flag
186 eMMC high-speed DDR mode (1.2V I/O) is supported.
188 mmc-ddr-1_8v:
189 $ref: /schemas/types.yaml#/definitions/flag
191 eMMC high-speed DDR mode (1.8V I/O) is supported.
193 mmc-ddr-3_3v:
194 $ref: /schemas/types.yaml#/definitions/flag
196 eMMC high-speed DDR mode (3.3V I/O) is supported.
198 mmc-hs200-1_2v:
199 $ref: /schemas/types.yaml#/definitions/flag
201 eMMC HS200 mode (1.2V I/O) is supported.
203 mmc-hs200-1_8v:
204 $ref: /schemas/types.yaml#/definitions/flag
206 eMMC HS200 mode (1.8V I/O) is supported.
208 mmc-hs400-1_2v:
209 $ref: /schemas/types.yaml#/definitions/flag
211 eMMC HS400 mode (1.2V I/O) is supported.
213 mmc-hs400-1_8v:
214 $ref: /schemas/types.yaml#/definitions/flag
216 eMMC HS400 mode (1.8V I/O) is supported.
218 mmc-hs400-enhanced-strobe:
219 $ref: /schemas/types.yaml#/definitions/flag
221 eMMC HS400 enhanced strobe mode is supported
223 no-mmc-hs400:
224 $ref: /schemas/types.yaml#/definitions/flag
236 no-sdio:
237 $ref: /schemas/types.yaml#/definitions/flag
242 no-sd:
243 $ref: /schemas/types.yaml#/definitions/flag
247 no-mmc:
248 $ref: /schemas/types.yaml#/definitions/flag
253 fixed-emmc-driver-type:
255 For non-removable eMMC, enforce this driver type. The value is
262 post-power-on-delay-ms:
264 It was invented for MMC pwrseq-simple which could be referred to
265 mmc-pwrseq-simple.txt. But now it\'s reused as a tunable delay
267 regardless of whether pwrseq-simple is used. Default to 10ms if
271 supports-cqe:
272 $ref: /schemas/types.yaml#/definitions/flag
277 disable-cqe-dcmd:
278 $ref: /schemas/types.yaml#/definitions/flag
284 keep-power-in-suspend:
285 $ref: /schemas/types.yaml#/definitions/flag
289 # Deprecated: enable-sdio-wakeup
290 wakeup-source:
291 $ref: /schemas/types.yaml#/definitions/flag
295 vmmc-supply:
299 vqmmc-supply:
303 mmc-pwrseq:
306 System-on-Chip designs may specify a specific MMC power
311 "^.*@[0-9]+$":
329 - minimum: 0
336 broken-hpi:
337 $ref: /schemas/types.yaml#/definitions/flag
339 Use this to indicate that the mmc-card has a broken hpi
343 - reg
345 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
346 $ref: /schemas/types.yaml#/definitions/uint32-array
355 controller while switching to particular speed mode. These values
359 cd-debounce-delay-ms: [ cd-gpios ]
360 fixed-emmc-driver-type: [ non-removable ]
365 - |
367 #address-cells = <1>;
368 #size-cells = <0>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&mmc3_pins_a>;
372 vmmc-supply = <®_vmmc3>;
373 bus-width = <4>;
374 non-removable;
375 mmc-pwrseq = <&sdhci0_pwrseq>;
379 compatible = "brcm,bcm4329-fmac";
380 interrupt-parent = <&pio>;
382 interrupt-names = "host-wake";