Lines Matching full:usdhc
30 - fsl,imx6q-usdhc
31 - fsl,imx6sl-usdhc
32 - fsl,imx6sll-usdhc
33 - fsl,imx6sx-usdhc
34 - fsl,imx6ull-usdhc
35 - fsl,imx7d-usdhc
36 - fsl,imx7ulp-usdhc
39 - fsl,imx8mm-usdhc
40 - fsl,imx8mn-usdhc
41 - fsl,imx8mp-usdhc
42 - fsl,imx8mq-usdhc
43 - fsl,imx8qm-usdhc
44 - fsl,imx8qxp-usdhc
45 - const: fsl,imx7d-usdhc
64 due to signal path is too long on the board. Please refer to eSDHC/uSDHC
91 The uSDHC use one delay cell as default increasing step to do tuning process.