Lines Matching +full:sig +full:- +full:dir +full:- +full:dat2
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Ulf Hansson <ulf.hansson@linaro.org>
20 - $ref: /schemas/arm/primecell.yaml#
21 - $ref: mmc-controller.yaml#
29 - arm,pl180
30 - arm,pl181
31 - arm,pl18x
33 - compatible
38 - description: The first version of the block, simply called
41 - const: arm,pl180
42 - const: arm,primecell
43 - description: The improved version of the block, found in the
48 - const: arm,pl181
49 - const: arm,primecell
50 - description: Wildcard entry that will let the operating system
54 - const: arm,pl18x
55 - const: arm,primecell
63 power-domains: true
84 st,sig-dir-dat0:
86 description: ST Micro-specific property, bus signal direction pins used for
89 st,sig-dir-dat2:
91 description: ST Micro-specific property, bus signal direction pins used for
94 st,sig-dir-dat31:
96 description: ST Micro-specific property, bus signal direction pins used for
99 st,sig-dir-dat74:
101 description: ST Micro-specific property, bus signal direction pins used for
104 st,sig-dir-cmd:
106 description: ST Micro-specific property, CMD signal direction used for
109 st,sig-pin-fbclk:
111 description: ST Micro-specific property, feedback clock FBCLK signal pin
114 st,sig-dir:
116 description: ST Micro-specific property, signal direction polarity used for
119 st,neg-edge:
121 description: ST Micro-specific property, data and command phase relation,
124 st,use-ckin:
126 description: ST Micro-specific property, use CKIN pin from an external
130 st,cmd-gpios:
135 st,ck-gpios:
140 st,ckin-gpios:
146 st,cmd-gpios: [ "st,use-ckin" ]
147 st,ck-gpios: [ "st,use-ckin" ]
148 st,ckin-gpios: [ "st,use-ckin" ]
153 - compatible
154 - reg
155 - interrupts
158 - |
159 #include <dt-bindings/interrupt-controller/irq.h>
160 #include <dt-bindings/gpio/gpio.h>
165 interrupts-extended = <&vic 22 &sic 1>;
167 clock-names = "mclk", "apb_pclk";
175 dma-names = "rx", "tx";
177 clock-names = "sdi", "apb_pclk";
178 max-frequency = <100000000>;
179 bus-width = <4>;
180 cap-sd-highspeed;
181 cap-mmc-highspeed;
182 cd-gpios = <&gpio2 31 0x4>;
183 st,sig-dir-dat0;
184 st,sig-dir-dat2;
185 st,sig-dir-cmd;
186 st,sig-pin-fbclk;
187 vmmc-supply = <&ab8500_ldo_aux3_reg>;
188 vqmmc-supply = <&vmmci>;
195 clock-names = "mclk", "apb_pclk";
196 interrupt-parent = <&vica>;
198 max-frequency = <400000>;
199 bus-width = <4>;
200 cap-mmc-highspeed;
201 cap-sd-highspeed;
202 full-pwr-cycle;
203 st,sig-dir-dat0;
204 st,sig-dir-dat2;
205 st,sig-dir-dat31;
206 st,sig-dir-cmd;
207 st,sig-pin-fbclk;
208 vmmc-supply = <&vmmc_regulator>;
213 arm,primecell-periphid = <0x10153180>;
216 interrupt-names = "cmd_irq";
218 clock-names = "apb_pclk";
220 cap-sd-highspeed;
221 cap-mmc-highspeed;
222 max-frequency = <120000000>;