Lines Matching +full:ch3 +full:- +full:0
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - advanced-control timers consist of a 16-bit auto-reload counter driven
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
16 - basic timers consist of a 16-bit auto-reload counter driven by a
20 - Benjamin Gaignard <benjamin.gaignard@st.com>
21 - Fabrice Gasnier <fabrice.gasnier@st.com>
25 const: st,stm32-timers
33 clock-names:
35 - const: int
44 dma-names:
46 enum: [ ch1, ch2, ch3, ch4, up, trig, com ]
50 "#address-cells":
53 "#size-cells":
54 const: 0
61 const: st,stm32-pwm
63 "#pwm-cells":
70 $ref: /schemas/types.yaml#/definitions/uint32-matrix
73 - description: |
74 "index" indicates on which break input (0 or 1) the
76 enum: [0, 1]
77 - description: |
78 "level" gives the active level (0=low or 1=high) of the
80 enum: [0, 1]
81 - description: |
88 - "#pwm-cells"
89 - compatible
92 "^timer@[0-9]+$":
98 - st,stm32-timer-trigger
99 - st,stm32h7-timer-trigger
104 minimum: 0
108 - compatible
109 - reg
116 const: st,stm32-timer-counter
119 - compatible
122 - compatible
123 - reg
124 - clocks
125 - clock-names
130 - |
131 #include <dt-bindings/clock/stm32mp1-clks.h>
133 #address-cells = <1>;
134 #size-cells = <0>;
135 compatible = "st,stm32-timers";
136 reg = <0x40000000 0x400>;
138 clock-names = "int";
139 dmas = <&dmamux1 18 0x400 0x1>,
140 <&dmamux1 19 0x400 0x1>,
141 <&dmamux1 20 0x400 0x1>,
142 <&dmamux1 21 0x400 0x1>,
143 <&dmamux1 22 0x400 0x1>;
144 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
146 compatible = "st,stm32-pwm";
147 #pwm-cells = <3>;
148 st,breakinput = <0 1 5>;
151 compatible = "st,stm32-timer-trigger";
155 compatible = "st,stm32-timer-counter";