Lines Matching +full:devfreq +full:- +full:events
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
13 - Lukasz Luba <lukasz.luba@arm.com>
27 - const: samsung,exynos5422-dmc
29 clock-names:
31 - const: fout_spll
32 - const: mout_sclk_spll
33 - const: ff_dout_spll2
34 - const: fout_bpll
35 - const: mout_bpll
36 - const: sclk_bpll
37 - const: mout_mx_mspll_ccore
38 - const: mout_mclk_cdrex
44 devfreq-events:
45 $ref: '/schemas/types.yaml#/definitions/phandle-array'
48 description: phandles of the PPMU events used by the controller.
50 device-handle:
56 operating-points-v2: true
60 - description: DMC internal performance event counters in DREX0
61 - description: DMC internal performance event counters in DREX1
63 interrupt-names:
65 - const: drex_0
66 - const: drex_1
70 - description: registers of DREX0
71 - description: registers of DREX1
73 samsung,syscon-clk:
81 vdd-supply: true
84 - compatible
85 - clock-names
86 - clocks
87 - devfreq-events
88 - device-handle
89 - reg
90 - samsung,syscon-clk
95 - |
96 #include <dt-bindings/clock/exynos5420.h>
98 compatible = "samsung,exynos-ppmu";
101 clock-names = "ppmu";
102 events {
103 ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {
104 event-name = "ppmu-event3-dmc0_0";
109 memory-controller@10c20000 {
110 compatible = "samsung,exynos5422-dmc";
120 clock-names = "fout_spll",
128 operating-points-v2 = <&dmc_opp_table>;
129 devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
131 device-handle = <&samsung_K3QF2F20DB>;
132 vdd-supply = <&buck1_reg>;
133 samsung,syscon-clk = <&clock>;
134 interrupt-parent = <&combiner>;
136 interrupt-names = "drex_0", "drex_1";