Lines Matching +full:external +full:- +full:memory +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 SoC External Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
16 service the request stream sent from Memory Controller. The EMC also has
17 various performance-affecting settings beyond the obvious SDRAM configuration
23 const: nvidia,tegra20-emc
34 "#address-cells":
37 "#size-cells":
40 "#interconnect-cells":
43 nvidia,memory-controller:
46 Phandle of the Memory Controller node.
48 power-domains:
53 operating-points-v2:
55 Should contain freqs and voltages and opp-supported-hw property, which
58 nvidia,use-ram-code:
61 If present, the emc-tables@ sub-nodes will be addressed.
64 emc-table:
68 const: nvidia,tegra20-emc-table
70 clock-frequency:
72 Memory clock rate in kHz.
82 nvidia,emc-registers:
87 $ref: /schemas/types.yaml#/definitions/uint32-array
89 - description: EMC_RC
90 - description: EMC_RFC
91 - description: EMC_RAS
92 - description: EMC_RP
93 - description: EMC_R2W
94 - description: EMC_W2R
95 - description: EMC_R2P
96 - description: EMC_W2P
97 - description: EMC_RD_RCD
98 - description: EMC_WR_RCD
99 - description: EMC_RRD
100 - description: EMC_REXT
101 - description: EMC_WDV
102 - description: EMC_QUSE
103 - description: EMC_QRST
104 - description: EMC_QSAFE
105 - description: EMC_RDV
106 - description: EMC_REFRESH
107 - description: EMC_BURST_REFRESH_NUM
108 - description: EMC_PDEX2WR
109 - description: EMC_PDEX2RD
110 - description: EMC_PCHG2PDEN
111 - description: EMC_ACT2PDEN
112 - description: EMC_AR2PDEN
113 - description: EMC_RW2PDEN
114 - description: EMC_TXSR
115 - description: EMC_TCKE
116 - description: EMC_TFAW
117 - description: EMC_TRPAB
118 - description: EMC_TCLKSTABLE
119 - description: EMC_TCLKSTOP
120 - description: EMC_TREFBW
121 - description: EMC_QUSE_EXTRA
122 - description: EMC_FBIO_CFG6
123 - description: EMC_ODT_WRITE
124 - description: EMC_ODT_READ
125 - description: EMC_FBIO_CFG5
126 - description: EMC_CFG_DIG_DLL
127 - description: EMC_DLL_XFORM_DQS
128 - description: EMC_DLL_XFORM_QUSE
129 - description: EMC_ZCAL_REF_CNT
130 - description: EMC_ZCAL_WAIT_CNT
131 - description: EMC_AUTO_CAL_INTERVAL
132 - description: EMC_CFG_CLKTRIM_0
133 - description: EMC_CFG_CLKTRIM_1
134 - description: EMC_CFG_CLKTRIM_2
137 - clock-frequency
138 - compatible
139 - reg
140 - nvidia,emc-registers
145 "^emc-table@[0-9]+$":
146 $ref: "#/$defs/emc-table"
148 "^emc-tables@[a-z0-9-]+$":
156 nvidia,ram-code:
161 "#address-cells":
164 "#size-cells":
168 "^emc-table@[0-9]+$":
169 $ref: "#/$defs/emc-table"
172 - nvidia,ram-code
177 - compatible
178 - reg
179 - interrupts
180 - clocks
181 - nvidia,memory-controller
182 - "#interconnect-cells"
183 - operating-points-v2
188 - |
189 external-memory-controller@7000f400 {
190 compatible = "nvidia,tegra20-emc";
195 nvidia,memory-controller = <&mc>;
196 operating-points-v2 = <&dvfs_opp_table>;
197 power-domains = <&domain>;
199 #interconnect-cells = <0>;
200 #address-cells = <1>;
201 #size-cells = <0>;
203 nvidia,use-ram-code;
205 emc-tables@0 {
206 nvidia,ram-code = <0>;
209 #address-cells = <1>;
210 #size-cells = <0>;
212 emc-table@333000 {
214 compatible = "nvidia,tegra20-emc-table";
215 clock-frequency = <333000>;
216 nvidia,emc-registers = <0x00000018 0x00000033