Lines Matching +full:apb +full:- +full:base
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
22 register which control the iommu port is at each larb's register base. But
23 for generation 1, the register is at smi ao base(smi always on register
24 base). Besides that, the smi async clock should be prepared and enabled for
31 - enum:
32 - mediatek,mt2701-smi-common
33 - mediatek,mt2712-smi-common
34 - mediatek,mt6779-smi-common
35 - mediatek,mt8167-smi-common
36 - mediatek,mt8173-smi-common
37 - mediatek,mt8183-smi-common
38 - mediatek,mt8192-smi-common
40 - description: for mt7623
42 - const: mediatek,mt7623-smi-common
43 - const: mediatek,mt2701-smi-common
48 power-domains:
53 apb and smi are mandatory. the async is only for generation 1 smi HW.
57 - description: apb is Advanced Peripheral Bus clock, It's the clock for
59 - description: smi is the clock for transfer data and command.
60 - description: Either asynchronous clock to help transform the smi clock
62 - description: gals1 is the path1 clock of gals.
64 clock-names:
69 - compatible
70 - reg
71 - power-domains
72 - clocks
73 - clock-names
76 - if: # only for gen1 HW
81 - mediatek,mt2701-smi-common
88 clock-names:
90 - const: apb
91 - const: smi
92 - const: async
94 - if: # for gen2 HW that have gals
98 - mediatek,mt6779-smi-common
99 - mediatek,mt8183-smi-common
100 - mediatek,mt8192-smi-common
108 clock-names:
110 - const: apb
111 - const: smi
112 - const: gals0
113 - const: gals1
121 clock-names:
123 - const: apb
124 - const: smi
129 - |+
130 #include <dt-bindings/clock/mt8173-clk.h>
131 #include <dt-bindings/power/mt8173-power.h>
134 compatible = "mediatek,mt8173-smi-common";
136 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
139 clock-names = "apb", "smi";