Lines Matching full:plic
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
26 with priority below this threshold will not cause the PLIC to raise its
29 While the PLIC supports both edge-triggered and level-triggered interrupts,
31 specified in the PLIC device-tree binding.
33 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
34 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
47 - sifive,fu540-c000-plic
48 - canaan,k210-plic
49 - const: sifive,plic-1.0.0
65 Specifies which contexts are connected to the PLIC, with "-1" specifying
87 plic: interrupt-controller@c000000 {
90 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";