Lines Matching +full:fu540 +full:- +full:c000

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11   SiFive SoCs and other RISC-V SoCs include an implementation of the
12   Platform-Level Interrupt Controller (PLIC) high-level specification in
13   the RISC-V Privileged Architecture specification. The PLIC connects all
18   in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21   Each interrupt can be enabled on per-context basis. Any context can claim
29   While the PLIC supports both edge-triggered and level-triggered interrupts,
31   specified in the PLIC device-tree binding.
33   While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
34   "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
36   SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
39   - Sagar Kadam <sagar.kadam@sifive.com>
40   - Paul Walmsley  <paul.walmsley@sifive.com>
41   - Palmer Dabbelt <palmer@dabbelt.com>
46       - enum:
47           - sifive,fu540-c000-plic
48           - canaan,k210-plic
49       - const: sifive,plic-1.0.0
54   '#address-cells':
57   '#interrupt-cells':
60   interrupt-controller: true
62   interrupts-extended:
65       Specifies which contexts are connected to the PLIC, with "-1" specifying
67       riscv,cpu-intc node, which has a riscv node as parent.
75   - compatible
76   - '#address-cells'
77   - '#interrupt-cells'
78   - interrupt-controller
79   - reg
80   - interrupts-extended
81   - riscv,ndev
86   - |
87     plic: interrupt-controller@c000000 {
88       #address-cells = <0>;
89       #interrupt-cells = <1>;
90       compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
91       interrupt-controller;
92       interrupts-extended = <