Lines Matching +full:msi +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller v1 and v2
10 - Marc Zyngier <marc.zyngier@arm.com>
18 Secondary GICs are cascaded into the upward interrupt controller and do not
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
35 - arm,gic-400
36 - arm,pl390
37 - arm,tc11mp-gic
38 - qcom,msm-8660-qgic
39 - qcom,msm-qgic2
41 - items:
42 - const: arm,gic-400
43 - enum:
44 - arm,cortex-a15-gic
45 - arm,cortex-a7-gic
47 - items:
48 - const: arm,arm1176jzf-devchip-gic
49 - const: arm,arm11mp-gic
51 - items:
52 - const: brcm,brahma-b15-gic
53 - const: arm,cortex-a15-gic
55 - oneOf:
56 - const: nvidia,tegra210-agic
57 - items:
58 - enum:
59 - nvidia,tegra186-agic
60 - nvidia,tegra194-agic
61 - const: nvidia,tegra210-agic
63 interrupt-controller: true
65 "#address-cells":
67 "#size-cells":
70 "#interrupt-cells":
77 SPI interrupts are in the range [0-987]. PPI interrupts are in the
78 range [0-15].
82 1 = low-to-high edge triggered
83 2 = high-to-low edge triggered (invalid for SPIs)
84 4 = active high level-sensitive
85 8 = active low level-sensitive (invalid for SPIs).
111 description: Interrupt source of the parent interrupt controller on
116 cpu-offset:
117 description: per-cpu offset within the distributor and cpu interface
119 is cpu-offset * cpu-nr.
126 clock-names:
130 - const: ic_clk # for "arm,arm11mp-gic"
131 - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
132 - items: # for "arm,cortex-a9-gic"
133 - const: PERIPHCLK
134 - const: PERIPHCLKEN
135 - const: clk # for "arm,gic-400" and "nvidia,tegra210"
136 - const: gclk #for "arm,pl390"
138 power-domains:
145 - compatible
146 - reg
149 "^v2m@[0-9a-f]+$":
152 * GICv2m extension for MSI/MSI-x support (Optional)
154 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
155 This is enabled by specifying v2m sub-node(s).
159 const: arm,gic-v2m-frame
161 msi-controller: true
165 description: GICv2m MSI interface register base and size
167 arm,msi-base-spi:
169 this property should contain the SPI base of the MSI frame, overriding
173 arm,msi-num-spis:
180 - compatible
181 - msi-controller
182 - reg
189 - |
191 intc: interrupt-controller@fff11000 {
192 compatible = "arm,cortex-a9-gic";
193 #interrupt-cells = <3>;
194 #address-cells = <1>;
195 interrupt-controller;
200 - |
202 interrupt-controller@2c001000 {
203 compatible = "arm,cortex-a15-gic";
204 #interrupt-cells = <3>;
205 interrupt-controller;
213 - |
214 // GICv2m extension for MSI/MSI-x support
215 interrupt-controller@e1101000 {
216 compatible = "arm,gic-400";
217 #interrupt-cells = <3>;
218 #address-cells = <1>;
219 #size-cells = <1>;
220 interrupt-controller;
229 compatible = "arm,gic-v2m-frame";
230 msi-controller;
237 compatible = "arm,gic-v2m-frame";
238 msi-controller;