Lines Matching +full:interrupts +full:- +full:extended
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
16 Interrupts (LPI).
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
27 - const: arm,gic-v3
28 - const: arm,gic-v3
30 interrupt-controller: true
32 "#address-cells":
34 "#size-cells":
39 "#interrupt-cells":
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
47 interrupts, 2 for interrupts in the Extended SPI range, 3 for the
48 Extended PPI range. Other values are reserved for future use.
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extented SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
62 pointed must be a subnode of the "ppi-partitions" subnode. For
64 this cell must be zero. See the "ppi-partitions" node description
75 - GIC Distributor interface (GICD)
76 - GIC Redistributors (GICR), one range per redistributor region
77 - GIC CPU interface (GICC)
78 - GIC Hypervisor interface (GICH)
79 - GIC Virtual CPU interface (GICV)
85 interrupts:
90 redistributor-stride:
98 "#redistributor-regions":
105 msi-controller:
108 being exposed by the HW, and the mbi-ranges property present.
110 mbi-ranges:
115 $ref: /schemas/types.yaml#/definitions/uint32-matrix
120 mbi-alias:
125 $ref: /schemas/types.yaml#/definitions/uint32-array
130 ppi-partitions:
133 PPI affinity can be expressed as a single "ppi-partitions" node,
134 containing a set of sub-nodes.
136 "^interrupt-partition-[0-9]+$":
140 $ref: /schemas/types.yaml#/definitions/phandle-array
146 - affinity
151 clock-names:
153 - const: aclk
155 power-domains:
162 mbi-ranges: [ msi-controller ]
163 msi-controller: [ mbi-ranges ]
166 - compatible
167 - interrupts
168 - reg
171 "^gic-its@": false
172 "^interrupt-controller@[0-9a-f]+$": false
173 # msi-controller is preferred, but allow other names
174 "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
178 used to route Message Signalled Interrupts (MSI) to the CPUs.
181 const: arm,gic-v3-its
183 msi-controller: true
185 "#msi-cells":
187 The single msi-cell is the DeviceID of the device which will generate
196 socionext,synquacer-pre-its:
199 address and size of the pre-ITS window.
200 $ref: /schemas/types.yaml#/definitions/uint32-array
206 - compatible
207 - msi-controller
208 - "#msi-cells"
209 - reg
216 - |
217 gic: interrupt-controller@2cf00000 {
218 compatible = "arm,gic-v3";
219 #interrupt-cells = <3>;
220 #address-cells = <1>;
221 #size-cells = <1>;
223 interrupt-controller;
229 interrupts = <1 9 4>;
231 msi-controller;
232 mbi-ranges = <256 128>;
234 msi-controller@2c200000 {
235 compatible = "arm,gic-v3-its";
236 msi-controller;
237 #msi-cells = <1>;
242 interrupt-controller@2c010000 {
243 compatible = "arm,gic-v3";
244 #interrupt-cells = <4>;
245 #address-cells = <1>;
246 #size-cells = <1>;
248 interrupt-controller;
249 redistributor-stride = <0x0 0x40000>; // 256kB stride
250 #redistributor-regions = <2>;
252 <0x2d000000 0x800000>, // GICR 1: CPUs 0-31
253 <0x2e000000 0x800000>, // GICR 2: CPUs 32-63
257 interrupts = <1 9 4>;
259 msi-controller@2c200000 {
260 compatible = "arm,gic-v3-its";
261 msi-controller;
262 #msi-cells = <1>;
266 msi-controller@2c400000 {
267 compatible = "arm,gic-v3-its";
268 msi-controller;
269 #msi-cells = <1>;
273 ppi-partitions {
274 part0: interrupt-partition-0 {
278 part1: interrupt-partition-1 {
287 interrupts = <1 1 4 &part0>;