Lines Matching +full:stm32mp1 +full:- +full:clks
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
29 - st,stm32mp1-adc-core
37 - stm32f4 and stm32h7 share a common ADC interrupt line.
38 - stm32mp1 has two separate interrupt lines, one for each ADC within
48 - "adc" clock: for the analog circuitry, common to all ADCs.
50 It's optional on stm32h7 and stm32mp1.
51 - "bus" clock: for registers access, common to all ADCs.
53 It's required on stm32h7 and stm32mp1.
55 clock-names: true
57 st,max-clk-rate-hz:
61 vdda-supply:
64 vref-supply:
67 booster-supply:
70 analog input switches on stm32h7 and stm32mp1.
72 vdd-supply:
75 input switches on stm32mp1.
80 analog circuitry on stm32mp1.
81 $ref: "/schemas/types.yaml#/definitions/phandle-array"
83 interrupt-controller: true
85 '#interrupt-cells':
88 '#address-cells':
91 '#size-cells':
95 - if:
99 const: st,stm32f4-adc-core
106 clock-names:
111 - description: interrupt line common for all ADCs
113 st,max-clk-rate-hz:
118 booster-supply: false
120 vdd-supply: false
124 - if:
128 const: st,stm32h7-adc-core
136 clock-names:
138 - const: bus
139 - const: adc
145 - description: interrupt line common for all ADCs
147 st,max-clk-rate-hz:
152 vdd-supply: false
156 - if:
160 const: st,stm32mp1-adc-core
168 clock-names:
170 - const: bus
171 - const: adc
177 - description: interrupt line for ADC1
178 - description: interrupt line for ADC2
180 st,max-clk-rate-hz:
188 - compatible
189 - reg
190 - interrupts
191 - clocks
192 - clock-names
193 - vdda-supply
194 - vref-supply
195 - interrupt-controller
196 - '#interrupt-cells'
197 - '#address-cells'
198 - '#size-cells'
201 "^adc@[0-9]+$":
210 - st,stm32f4-adc
211 - st,stm32h7-adc
212 - st,stm32mp1-adc
217 - 0x0: ADC1
218 - 0x100: ADC2
219 - 0x200: ADC3 (stm32f4 only)
222 '#io-channel-cells':
228 - 0 for adc@0
229 - 1 for adc@100
230 - 2 for adc@200 (stm32f4 only)
243 dma-names:
246 assigned-resolution-bits:
249 - can be 6, 8, 10 or 12 on stm32f4
250 - can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
252 st,adc-channels:
254 List of single-ended channels muxed for this ADC. It can have up to:
255 - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
256 - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
257 stm32mp1.
258 $ref: /schemas/types.yaml#/definitions/uint32-array
260 st,adc-diff-channels:
263 be configured as differential instead of single-ended on stm32h7 and
264 on stm32mp1. Positive and negative inputs pairs are listed:
267 Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
269 used as single-ended and some other ones as differential (mixed). But
270 channels can't be configured both as single-ended and differential.
271 $ref: /schemas/types.yaml#/definitions/uint32-matrix
274 - description: |
278 - description: |
283 st,min-sample-time-nsecs:
288 array that matches "st,adc-channels" and/or "st,adc-diff-channels"
291 $ref: /schemas/types.yaml#/definitions/uint32-array
294 - if:
298 const: st,stm32f4-adc
304 - 0x0
305 - 0x100
306 - 0x200
312 assigned-resolution-bits:
316 st,adc-channels:
323 st,adc-diff-channels: false
325 st,min-sample-time-nsecs:
332 - clocks
334 - if:
339 - st,stm32h7-adc
340 - st,stm32mp1-adc
346 - 0x0
347 - 0x100
353 assigned-resolution-bits:
357 st,adc-channels:
364 st,min-sample-time-nsecs:
373 - required:
374 - st,adc-channels
375 - required:
376 - st,adc-diff-channels
379 - compatible
380 - reg
381 - interrupts
382 - '#io-channel-cells'
385 - |
386 // Example 1: with stm32f429, ADC1, single-ended channel 8
388 compatible = "st,stm32f4-adc-core";
392 clock-names = "adc";
393 st,max-clk-rate-hz = <36000000>;
394 vdda-supply = <&vdda>;
395 vref-supply = <&vref>;
396 interrupt-controller;
397 #interrupt-cells = <1>;
398 #address-cells = <1>;
399 #size-cells = <0>;
401 compatible = "st,stm32f4-adc";
402 #io-channel-cells = <1>;
405 interrupt-parent = <&adc123>;
407 st,adc-channels = <8>;
409 dma-names = "rx";
410 assigned-resolution-bits = <8>;
416 - |
418 // - channels 0 & 1 as single-ended
419 // - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
420 #include <dt-bindings/interrupt-controller/arm-gic.h>
421 #include <dt-bindings/clock/stm32mp1-clks.h>
423 compatible = "st,stm32mp1-adc-core";
428 clock-names = "bus", "adc";
429 booster-supply = <&booster>;
430 vdd-supply = <&vdd>;
431 vdda-supply = <&vdda>;
432 vref-supply = <&vref>;
434 interrupt-controller;
435 #interrupt-cells = <1>;
436 #address-cells = <1>;
437 #size-cells = <0>;
439 compatible = "st,stm32mp1-adc";
440 #io-channel-cells = <1>;
442 interrupt-parent = <&adc12>;
444 st,adc-channels = <0 1>;
445 st,adc-diff-channels = <2 6>, <3 7>;
446 st,min-sample-time-nsecs = <5000>;
448 dma-names = "rx";