Lines Matching +full:assigned +full:- +full:clock +full:- +full:parents
1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <mkrishn@codeaurora.org>
13 - $ref: "../dsi-controller.yaml#"
18 - const: qcom,mdss-dsi-ctrl
23 reg-names:
31 - description: Display byte clock
32 - description: Display byte interface clock
33 - description: Display pixel clock
34 - description: Display escape clock
35 - description: Display AHB clock
36 - description: Display AXI clock
38 clock-names:
40 - const: byte
41 - const: byte_intf
42 - const: pixel
43 - const: core
44 - const: iface
45 - const: bus
50 phy-names:
53 "#address-cells": true
55 "#size-cells": true
57 syscon-sfpb:
61 qcom,dual-dsi-mode:
67 assigned-clocks:
71 Parents of "byte" and "pixel" for the given platform.
73 assigned-clock-parents:
77 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
79 power-domains:
82 operating-points-v2: true
92 $ref: "/schemas/graph.yaml#/$defs/port-base"
98 $ref: /schemas/media/video-interfaces.yaml#
101 data-lanes:
108 $ref: "/schemas/graph.yaml#/$defs/port-base"
114 $ref: /schemas/media/video-interfaces.yaml#
117 data-lanes:
124 - port@0
125 - port@1
128 - compatible
129 - reg
130 - reg-names
131 - interrupts
132 - clocks
133 - clock-names
134 - phys
135 - phy-names
136 - assigned-clocks
137 - assigned-clock-parents
138 - power-domains
139 - operating-points-v2
140 - ports
145 - |
146 #include <dt-bindings/interrupt-controller/arm-gic.h>
147 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
148 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
149 #include <dt-bindings/power/qcom-rpmpd.h>
152 compatible = "qcom,mdss-dsi-ctrl";
154 reg-names = "dsi_ctrl";
156 #address-cells = <1>;
157 #size-cells = <0>;
159 interrupt-parent = <&mdss>;
168 clock-names = "byte",
176 phy-names = "dsi";
178 … assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
179 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
181 power-domains = <&rpmhpd SC7180_CX>;
182 operating-points-v2 = <&dsi_opp_table>;
185 #address-cells = <1>;
186 #size-cells = <0>;
191 remote-endpoint = <&dpu_intf1_out>;
198 remote-endpoint = <&sn65dsi86_in>;
199 data-lanes = <0 1 2 3>;