Lines Matching +full:0 +full:x0ae94000

91       port@0:
105                   enum: [ 0, 1, 2, 3 ]
121                   enum: [ 0, 1, 2, 3 ]
124       - port@0
153            reg = <0x0ae94000 0x400>;
157            #size-cells = <0>;
179            assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
186                   #size-cells = <0>;
188                   port@0 {
189                           reg = <0>;
199                                    data-lanes = <0 1 2 3>;