Lines Matching +full:gcc +full:- +full:sc7180
1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SC7180 target
10 - Krishna Manikandan <mkrishn@codeaurora.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS and DPU are mentioned for SC7180 target.
20 - const: qcom,sc7180-mdss
25 reg-names:
28 power-domains:
33 - description: Display AHB clock from gcc
34 - description: Display AHB clock from dispcc
35 - description: Display core clock
37 clock-names:
39 - const: iface
40 - const: ahb
41 - const: core
46 interrupt-controller: true
48 "#address-cells": true
50 "#size-cells": true
52 "#interrupt-cells":
57 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
63 - description: Interconnect path specifying the port ids for data bus
65 interconnect-names:
66 const: mdp0-mem
69 "^display-controller@[0-9a-f]+$":
76 - const: qcom,sc7180-dpu
80 - description: Address offset and size for mdp register set
81 - description: Address offset and size for vbif register set
83 reg-names:
85 - const: mdp
86 - const: vbif
90 - description: Display hf axi clock
91 - description: Display ahb clock
92 - description: Display rotator clock
93 - description: Display lut clock
94 - description: Display core clock
95 - description: Display vsync clock
97 clock-names:
99 - const: bus
100 - const: iface
101 - const: rot
102 - const: lut
103 - const: core
104 - const: vsync
109 power-domains:
112 operating-points-v2: true
132 - port@0
135 - compatible
136 - reg
137 - reg-names
138 - clocks
139 - interrupts
140 - power-domains
141 - operating-points-v2
142 - ports
145 - compatible
146 - reg
147 - reg-names
148 - power-domains
149 - clocks
150 - interrupts
151 - interrupt-controller
152 - iommus
153 - ranges
158 - |
159 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
160 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
161 #include <dt-bindings/interrupt-controller/arm-gic.h>
162 #include <dt-bindings/interconnect/qcom,sdm845.h>
163 #include <dt-bindings/power/qcom-rpmpd.h>
165 display-subsystem@ae00000 {
166 #address-cells = <1>;
167 #size-cells = <1>;
168 compatible = "qcom,sc7180-mdss";
170 reg-names = "mdss";
171 power-domains = <&dispcc MDSS_GDSC>;
172 clocks = <&gcc GCC_DISP_AHB_CLK>,
175 clock-names = "iface", "ahb", "core";
178 interrupt-controller;
179 #interrupt-cells = <1>;
182 interconnect-names = "mdp0-mem";
187 display-controller@ae01000 {
188 compatible = "qcom,sc7180-dpu";
192 reg-names = "mdp", "vbif";
194 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
200 clock-names = "bus", "iface", "rot", "lut", "core",
203 interrupt-parent = <&mdss>;
205 power-domains = <&rpmhpd SC7180_CX>;
206 operating-points-v2 = <&mdp_opp_table>;
209 #address-cells = <1>;
210 #size-cells = <0>;
215 remote-endpoint = <&dsi0_in>;
222 remote-endpoint = <&dp_in>;