Lines Matching +full:clock +full:- +full:output +full:- +full:names
1 * Clock Block on Freescale QorIQ Platforms
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
29 * "fsl,p5020-clockgen"
30 * "fsl,p5040-clockgen"
31 * "fsl,t1023-clockgen"
32 * "fsl,t1024-clockgen"
33 * "fsl,t1040-clockgen"
34 * "fsl,t1042-clockgen"
35 * "fsl,t2080-clockgen"
36 * "fsl,t2081-clockgen"
37 * "fsl,t4240-clockgen"
38 * "fsl,b4420-clockgen"
39 * "fsl,b4860-clockgen"
40 * "fsl,ls1012a-clockgen"
41 * "fsl,ls1021a-clockgen"
42 * "fsl,ls1028a-clockgen"
43 * "fsl,ls1043a-clockgen"
44 * "fsl,ls1046a-clockgen"
45 * "fsl,ls1088a-clockgen"
46 * "fsl,ls2080a-clockgen"
47 Chassis-version clock strings include:
48 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
49 * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
50 - reg: Describes the address of the device's resources within the
52 represents the clock register set
55 - ranges: Allows valid translation between child's address space and
56 parent's. Must be present if the device has sub-nodes.
57 - #address-cells: Specifies the number of cells used to represent
59 sub-nodes and set to 1 if present
60 - #size-cells: Specifies the number of cells used to represent
62 sub-nodes and set to 1 if present
63 - clock-frequency: Input system clock frequency (SYSCLK)
64 - clocks: If clock-frequency is not specified, sysclk may be provided
65 as an input clock. Either clock-frequency or clocks must be
67 A second input clock, called "coreclk", may be provided if
68 core PLLs are based on a different input clock from the
70 - clock-names: Required if a coreclk is present. Valid names are
73 2. Clock Provider
75 The clockgen node should act as a clock provider, though in older device
76 trees the children of the clockgen node are the clock providers.
78 When the clockgen node is a clock provider, #clock-cells = <2>.
79 The first cell of the clock specifier is the clock type, and the
80 second cell is the clock index for the specified type.
93 clockgen: global-utilities@e1000 {
94 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
95 clock-frequency = <133333333>;
97 #clock-cells = <2>;
111 Most of the bindings are from the common clock binding[1].
112 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
115 - compatible : Should include one of the following:
116 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
117 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
118 * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
119 * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
120 * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
121 It takes parent's clock-frequency as its clock.
122 * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
123 It takes parent's clock-frequency as its clock.
124 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
125 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
126 - #clock-cells: From common clock binding. The number of cells in a
127 clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
128 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
129 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
130 clock-specifier cell may take the following values:
131 * 0 - equal to the PLL frequency
132 * 1 - equal to the PLL frequency divided by 2
133 * 2 - equal to the PLL frequency divided by 4
136 - clocks: Should be the phandle of input parent clock
137 - clock-names: From common clock binding, indicates the clock name
138 - clock-output-names: From common clock binding, indicates the names of
139 output clocks
140 - reg: Should be the offset and length of clock block base address.
145 clockgen: global-utilities@e1000 {
146 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
148 clock-frequency = <133333333>;
150 #address-cells = <1>;
151 #size-cells = <1>;
154 #clock-cells = <0>;
155 compatible = "fsl,qoriq-sysclk-1.0";
156 clock-output-names = "sysclk";
160 #clock-cells = <1>;
162 compatible = "fsl,qoriq-core-pll-1.0";
164 clock-output-names = "pll0", "pll0-div2";
168 #clock-cells = <1>;
170 compatible = "fsl,qoriq-core-pll-1.0";
172 clock-output-names = "pll1", "pll1-div2";
176 #clock-cells = <0>;
178 compatible = "fsl,qoriq-core-mux-1.0";
180 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
181 clock-output-names = "cmux0";
185 #clock-cells = <0>;
187 compatible = "fsl,qoriq-core-mux-1.0";
189 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
190 clock-output-names = "cmux1";
193 platform-pll: platform-pll@c00 {
194 #clock-cells = <1>;
196 compatible = "fsl,qoriq-platform-pll-1.0";
198 clock-output-names = "platform-pll", "platform-pll-div2";
203 Example for legacy clock consumer: