Lines Matching +full:displayport +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller Binding
10 - Jeffrey Hugo <jhugo@codeaurora.org>
11 - Taniya Das <tdas@codeaurora.org>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8660
23 - qcom,mmcc-msm8960
24 - qcom,mmcc-msm8974
25 - qcom,mmcc-msm8992
26 - qcom,mmcc-msm8994
27 - qcom,mmcc-msm8996
28 - qcom,mmcc-msm8998
29 - qcom,mmcc-sdm630
30 - qcom,mmcc-sdm660
34 - description: Board XO source
35 - description: Board sleep source
36 - description: Global PLL 0 clock
37 - description: DSI phy instance 0 dsi clock
38 - description: DSI phy instance 0 byte clock
39 - description: DSI phy instance 1 dsi clock
40 - description: DSI phy instance 1 byte clock
41 - description: HDMI phy PLL clock
42 - description: DisplayPort phy PLL vco clock
43 - description: DisplayPort phy PLL link clock
45 clock-names:
47 - const: xo
48 - const: sleep
49 - const: gpll0
50 - const: dsi0dsi
51 - const: dsi0byte
52 - const: dsi1dsi
53 - const: dsi1byte
54 - const: hdmipll
55 - const: dpvco
56 - const: dplink
58 '#clock-cells':
61 '#reset-cells':
64 '#power-domain-cells':
70 protected-clocks:
74 vdd-gfx-supply:
79 - compatible
80 - reg
81 - '#clock-cells'
82 - '#reset-cells'
83 - '#power-domain-cells'
91 const: qcom,mmcc-msm8998
95 - clocks
96 - clock-names
100 - |
101 clock-controller@4000000 {
102 compatible = "qcom,mmcc-msm8960";
104 #clock-cells = <1>;
105 #reset-cells = <1>;
106 #power-domain-cells = <1>;