Lines Matching +full:secure +full:- +full:monitor

1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Performance Monitor Units
10   - Mark Rutland <mark.rutland@arm.com>
11   - Will Deacon <will.deacon@arm.com>
16   representation in the device tree should be done as under:-
21       - enum:
22           - apm,potenza-pmu
23           - arm,armv8-pmuv3 # Only for s/w models
24           - arm,arm1136-pmu
25           - arm,arm1176-pmu
26           - arm,arm11mpcore-pmu
27           - arm,cortex-a5-pmu
28           - arm,cortex-a7-pmu
29           - arm,cortex-a8-pmu
30           - arm,cortex-a9-pmu
31           - arm,cortex-a12-pmu
32           - arm,cortex-a15-pmu
33           - arm,cortex-a17-pmu
34           - arm,cortex-a32-pmu
35           - arm,cortex-a34-pmu
36           - arm,cortex-a35-pmu
37           - arm,cortex-a53-pmu
38           - arm,cortex-a55-pmu
39           - arm,cortex-a57-pmu
40           - arm,cortex-a65-pmu
41           - arm,cortex-a72-pmu
42           - arm,cortex-a73-pmu
43           - arm,cortex-a75-pmu
44           - arm,cortex-a76-pmu
45           - arm,cortex-a77-pmu
46           - arm,cortex-a78-pmu
47           - arm,neoverse-e1-pmu
48           - arm,neoverse-n1-pmu
49           - brcm,vulcan-pmu
50           - cavium,thunder-pmu
51           - qcom,krait-pmu
52           - qcom,scorpion-pmu
53           - qcom,scorpion-mp-pmu
57     description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
59   interrupt-affinity:
60     $ref: /schemas/types.yaml#/definitions/phandle-array
71       the interrupt-affinity property shouldn't be present).
76   qcom,no-pc-write:
81   secure-reg-access:
84       Indicates that the ARMv7 Secure Debug Enable Register
86       any setup required that is only possible in ARMv7 secure
89       code (bootloader or security monitor) has performed the
91       not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
92       in Non-secure state.
95   - compatible