Lines Matching +full:cortex +full:- +full:a57
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
88 - apple,icestorm
89 - apple,firestorm
90 - arm,arm710t
91 - arm,arm720t
92 - arm,arm740t
93 - arm,arm7ej-s
94 - arm,arm7tdmi
95 - arm,arm7tdmi-s
96 - arm,arm9es
97 - arm,arm9ej-s
98 - arm,arm920t
99 - arm,arm922t
100 - arm,arm925
101 - arm,arm926e-s
102 - arm,arm926ej-s
103 - arm,arm940t
104 - arm,arm946e-s
105 - arm,arm966e-s
106 - arm,arm968e-s
107 - arm,arm9tdmi
108 - arm,arm1020e
109 - arm,arm1020t
110 - arm,arm1022e
111 - arm,arm1026ej-s
112 - arm,arm1136j-s
113 - arm,arm1136jf-s
114 - arm,arm1156t2-s
115 - arm,arm1156t2f-s
116 - arm,arm1176jzf
117 - arm,arm1176jz-s
118 - arm,arm1176jzf-s
119 - arm,arm11mpcore
120 - arm,armv8 # Only for s/w models
121 - arm,cortex-a5
122 - arm,cortex-a7
123 - arm,cortex-a8
124 - arm,cortex-a9
125 - arm,cortex-a12
126 - arm,cortex-a15
127 - arm,cortex-a17
128 - arm,cortex-a32
129 - arm,cortex-a34
130 - arm,cortex-a35
131 - arm,cortex-a53
132 - arm,cortex-a55
133 - arm,cortex-a57
134 - arm,cortex-a65
135 - arm,cortex-a72
136 - arm,cortex-a73
137 - arm,cortex-a75
138 - arm,cortex-a76
139 - arm,cortex-a77
140 - arm,cortex-m0
141 - arm,cortex-m0+
142 - arm,cortex-m1
143 - arm,cortex-m3
144 - arm,cortex-m4
145 - arm,cortex-r4
146 - arm,cortex-r5
147 - arm,cortex-r7
148 - arm,neoverse-e1
149 - arm,neoverse-n1
150 - brcm,brahma-b15
151 - brcm,brahma-b53
152 - brcm,vulcan
153 - cavium,thunder
154 - cavium,thunder2
155 - faraday,fa526
156 - intel,sa110
157 - intel,sa1100
158 - marvell,feroceon
159 - marvell,mohawk
160 - marvell,pj4a
161 - marvell,pj4b
162 - marvell,sheeva-v5
163 - marvell,sheeva-v7
164 - nvidia,tegra132-denver
165 - nvidia,tegra186-denver
166 - nvidia,tegra194-carmel
167 - qcom,krait
168 - qcom,kryo
169 - qcom,kryo260
170 - qcom,kryo280
171 - qcom,kryo385
172 - qcom,kryo468
173 - qcom,kryo485
174 - qcom,kryo685
175 - qcom,scorpion
177 enable-method:
180 # On ARM v8 64-bit this property is required
181 - enum:
182 - psci
183 - spin-table
184 # On ARM 32-bit systems this property is optional
185 - enum:
186 - actions,s500-smp
187 - allwinner,sun6i-a31
188 - allwinner,sun8i-a23
189 - allwinner,sun9i-a80-smp
190 - allwinner,sun8i-a83t-smp
191 - amlogic,meson8-smp
192 - amlogic,meson8b-smp
193 - arm,realview-smp
194 - aspeed,ast2600-smp
195 - brcm,bcm11351-cpu-method
196 - brcm,bcm23550
197 - brcm,bcm2836-smp
198 - brcm,bcm63138
199 - brcm,bcm-nsp-smp
200 - brcm,brahma-b15
201 - marvell,armada-375-smp
202 - marvell,armada-380-smp
203 - marvell,armada-390-smp
204 - marvell,armada-xp-smp
205 - marvell,98dx3236-smp
206 - marvell,mmp3-smp
207 - mediatek,mt6589-smp
208 - mediatek,mt81xx-tz-smp
209 - qcom,gcc-msm8660
210 - qcom,kpss-acc-v1
211 - qcom,kpss-acc-v2
212 - renesas,apmu
213 - renesas,r9a06g032-smp
214 - rockchip,rk3036-smp
215 - rockchip,rk3066-smp
216 - socionext,milbeaut-m10v-smp
217 - ste,dbx500-smp
218 - ti,am3352
219 - ti,am4372
221 cpu-release-addr:
225 Required for systems that have an "enable-method"
226 property value of "spin-table".
227 On ARM v8 64-bit systems must be a two cell
228 property identifying a 64-bit zero-initialised
231 cpu-idle-states:
232 $ref: '/schemas/types.yaml#/definitions/phandle-array'
235 by this cpu (see ./idle-states.yaml).
237 capacity-dmips-mhz:
239 u32 value representing CPU capacity (see ./cpu-capacity.txt) in
240 DMIPS/MHz, relative to highest capacity-dmips-mhz
243 dynamic-power-coefficient:
254 calculate the dynamic power as below -
256 Pdyn = dynamic-power-coefficient * V^2 * f
260 performance-domains:
265 dvfs/performance-domain.yaml.
267 power-domains:
272 power-domain-names:
275 power-domains property.
285 Required for systems that have an "enable-method" property
286 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
295 Required for systems that have an "enable-method" property
296 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
298 * arm/msm/qcom,kpss-acc.txt
305 Optional for systems that have an "enable-method"
306 property value of "rockchip,rk3066-smp"
308 the cpu-core power-domains.
310 secondary-boot-reg:
313 Required for systems that have an "enable-method" property value of
314 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
320 The secondary-boot-reg property is a u32 value that specifies the
327 # If the enable-method property contains one of those values
329 enable-method:
332 - brcm,bcm11351-cpu-method
333 - brcm,bcm23550
334 - brcm,bcm-nsp-smp
335 # and if enable-method is present
337 - enable-method
341 - secondary-boot-reg
344 - device_type
345 - reg
346 - compatible
349 rockchip,pmu: [enable-method]
354 - |
356 #size-cells = <0>;
357 #address-cells = <1>;
361 compatible = "arm,cortex-a15";
367 compatible = "arm,cortex-a15";
373 compatible = "arm,cortex-a7";
379 compatible = "arm,cortex-a7";
384 - |
385 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
387 #size-cells = <0>;
388 #address-cells = <1>;
392 compatible = "arm,cortex-a8";
397 - |
398 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
400 #size-cells = <0>;
401 #address-cells = <1>;
405 compatible = "arm,arm926ej-s";
410 - |
411 // Example 4 (ARM Cortex-A57 64-bit system):
413 #size-cells = <0>;
414 #address-cells = <2>;
418 compatible = "arm,cortex-a57";
420 enable-method = "spin-table";
421 cpu-release-addr = <0 0x20000000>;
426 compatible = "arm,cortex-a57";
428 enable-method = "spin-table";
429 cpu-release-addr = <0 0x20000000>;
434 compatible = "arm,cortex-a57";
436 enable-method = "spin-table";
437 cpu-release-addr = <0 0x20000000>;
442 compatible = "arm,cortex-a57";
444 enable-method = "spin-table";
445 cpu-release-addr = <0 0x20000000>;
450 compatible = "arm,cortex-a57";
452 enable-method = "spin-table";
453 cpu-release-addr = <0 0x20000000>;
458 compatible = "arm,cortex-a57";
460 enable-method = "spin-table";
461 cpu-release-addr = <0 0x20000000>;
466 compatible = "arm,cortex-a57";
468 enable-method = "spin-table";
469 cpu-release-addr = <0 0x20000000>;
474 compatible = "arm,cortex-a57";
476 enable-method = "spin-table";
477 cpu-release-addr = <0 0x20000000>;
482 compatible = "arm,cortex-a57";
484 enable-method = "spin-table";
485 cpu-release-addr = <0 0x20000000>;
490 compatible = "arm,cortex-a57";
492 enable-method = "spin-table";
493 cpu-release-addr = <0 0x20000000>;
498 compatible = "arm,cortex-a57";
500 enable-method = "spin-table";
501 cpu-release-addr = <0 0x20000000>;
506 compatible = "arm,cortex-a57";
508 enable-method = "spin-table";
509 cpu-release-addr = <0 0x20000000>;
514 compatible = "arm,cortex-a57";
516 enable-method = "spin-table";
517 cpu-release-addr = <0 0x20000000>;
522 compatible = "arm,cortex-a57";
524 enable-method = "spin-table";
525 cpu-release-addr = <0 0x20000000>;
530 compatible = "arm,cortex-a57";
532 enable-method = "spin-table";
533 cpu-release-addr = <0 0x20000000>;
538 compatible = "arm,cortex-a57";
540 enable-method = "spin-table";
541 cpu-release-addr = <0 0x20000000>;