Lines Matching +full:mode +full:- +full:loader
13 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
14 counterpart. EL2 is the hypervisor level and exists only in non-secure
15 mode. EL3 is the highest priority level and exists only in secure mode.
17 For the purposes of this document, we will use the term `boot loader`
23 Essentially, the boot loader should provide (as a minimum) the
33 ---------------------------
37 The boot loader is expected to find and initialise all RAM that the
41 the RAM in the machine, or any other method the boot loader designer
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
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65 loader if a compressed Image target (e.g. Image.gz) is used. For
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
91 - As of v3.17, all fields are little endian unless stated otherwise.
93 - code0/code1 are responsible for branching to stext.
95 - when booting through EFI, code0/code1 are initially skipped.
100 - Prior to v3.17, the endianness of text_offset was not specified. In
102 endianness of the kernel. Where image_size is non-zero image_size is
103 little-endian and must be respected. Where image_size is zero,
106 - The flags field (introduced in v3.17) is a little-endian 64-bit field
111 Bit 1-2 Kernel Page size.
113 * 0 - Unspecified.
114 * 1 - 4K
115 * 2 - 16K
116 * 3 - 64K
126 Bits 4-63 Reserved.
129 - When image_size is zero, a bootloader should attempt to keep as much
155 - Quiesce all DMA capable devices so that memory does not get
159 - Primary CPU general-purpose register settings:
161 - x0 = physical address of device tree blob (dtb) in system RAM.
162 - x1 = 0 (reserved for future use)
163 - x2 = 0 (reserved for future use)
164 - x3 = 0 (reserved for future use)
166 - CPU mode
171 the virtualisation extensions) or non-secure EL1.
173 - Caches, MMUs
189 - Architected timers
196 - Coherency
203 - System registers
211 - If EL3 is present:
213 - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
215 - The value of SCR_EL3.FIQ must be the same as the one present at boot
218 - If EL3 is present and the kernel is entered at EL2:
220 - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
222 For systems with a GICv3 interrupt controller to be used in v3 mode:
223 - If EL3 is present:
225 - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
226 - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
227 - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
231 - If the kernel is entered at EL1:
233 - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
234 - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
236 - The DT or ACPI tables must describe a GICv3 interrupt controller.
239 compatibility (v2) mode:
241 - If EL3 is present:
245 - If the kernel is entered at EL1:
249 - The DT or ACPI tables must describe a GICv2 interrupt controller.
253 - If EL3 is present:
255 - SCR_EL3.APK (bit 16) must be initialised to 0b1
256 - SCR_EL3.API (bit 17) must be initialised to 0b1
258 - If the kernel is entered at EL1:
260 - HCR_EL2.APK (bit 40) must be initialised to 0b1
261 - HCR_EL2.API (bit 41) must be initialised to 0b1
265 - If EL3 is present:
267 - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
268 - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
269 - AMCNTENSET0_EL0 must be initialised to 0b1111
270 - AMCNTENSET1_EL0 must be initialised to a platform specific value
274 - If the kernel is entered at EL1:
276 - AMCNTENSET0_EL0 must be initialised to 0b1111
277 - AMCNTENSET1_EL0 must be initialised to a platform specific value
283 - If EL3 is present and the kernel is entered at EL2:
285 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
289 - If EL3 is present and the kernel is entered at EL2:
291 - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
295 - If EL3 is present:
297 - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
299 - If EL2 is present and the kernel is entered at EL1:
301 - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
305 - if EL3 is present:
307 - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
309 - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
312 - If the kernel is entered at EL1 and EL2 is present:
314 - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
316 - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
318 - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
323 - If EL3 is present:
325 - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
327 - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
329 - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
332 - If the kernel is entered at EL1 and EL2 is present:
334 - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
336 - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
338 - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
340 - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
343 The requirements described above for CPU mode, caches, MMUs, architected
350 The boot loader is expected to enter the kernel on each CPU in the
353 - The primary CPU must jump directly to the first instruction of the
355 an 'enable-method' property for each cpu node. The supported
356 enable-methods are described below.
361 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
363 naturally-aligned 64-bit zero-initalised memory location.
367 device tree) polling their cpu-release-addr location, which must be
369 to reduce the overhead of the busy-loop and a sev will be issued by
371 cpu-release-addr returns a non-zero value, the CPU must jump to this
372 value. The value will be written as a single 64-bit little-endian
376 - CPUs with a "psci" enable method should remain outside of
387 - Secondary CPU general-purpose register settings
389 - x0 = 0 (reserved for future use)
390 - x1 = 0 (reserved for future use)
391 - x2 = 0 (reserved for future use)
392 - x3 = 0 (reserved for future use)