Lines Matching refs:PRIx64
709 …intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s hit filter: %s offset %#"PRIx64" size … in intel_pt_match_pgd_ip()
721 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s is not in a filter region\n", in intel_pt_match_pgd_ip()
1232 intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n", in intel_pt_setup_queue()
2239 intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n", in intel_pt_run_decoder()
2278 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n", in intel_pt_run_decoder()
2286 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n", in intel_pt_run_decoder()
2336 intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n", in intel_pt_process_queues()
2534 intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n", in intel_pt_process_switch()
2625 intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n", in intel_pt_process_itrace_start()
2688 intel_pt_log("Invalidated instruction cache for %s at %#"PRIx64"\n", in intel_pt_text_poke()
2768 intel_pt_log("event %u: cpu %d time %"PRIu64" tsc %#"PRIx64" ", in intel_pt_process_event()
2923 pr_debug("Synthesizing '%s' event with id %" PRIu64 " sample type %#" PRIx64 "\n", in intel_pt_synth_event()
3250 intel_pt_log("range %d: TSC time interval: %#"PRIx64" to %#"PRIx64"\n", in intel_pt_setup_time_ranges()
3263 [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n",
3264 [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n",
3268 [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n",
3271 [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n",