Lines Matching +full:front +full:- +full:end

27 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not …
40         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
46         "PublicDescription": "Cycles with less than 3 uops delivered by the front-end.",
68 …"PublicDescription": "Counts, on the per-thread basis, cycles when less than 1 uop is delivered to…
73 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc…
78 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
83 …Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) mi…
91 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
103 …"PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resour…
108 …d after an interval where the front-end delivered no uops for a period of 16 cycles which was not …
116 …ons that are delivered to the back-end after a front-end stall of at least 16 cycles. During this …
132         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
138         "PublicDescription": "Cycles with less than 2 uops delivered by the front-end.",
165 …etch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
210 …d after an interval where the front-end delivered no uops for a period of 64 cycles which was not …
228 …) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation T…
252         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
257 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
297 … after an interval where the front-end delivered no uops for a period of 512 cycles which was not …
310 …d after an interval where the front-end delivered no uops for a period of 8 cycles which was not i…
318 …ions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this …
324         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
332 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n…
338 …d after an interval where the front-end delivered no uops for a period of 2 cycles which was not i…
351 …d after an interval where the front-end delivered no uops for a period of 4 cycles which was not i…
396 … after an interval where the front-end delivered no uops for a period of 256 cycles which was not …
409 …er an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was …
422 …er an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was …
435 …ter an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was …
443 …delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles.…
460         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
465 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
470 …d after an interval where the front-end delivered no uops for a period of 32 cycles which was not …
478 …ons that are delivered to the back-end after a front-end stall of at least 32 cycles. During this …
495 …tch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity…