Lines Matching +full:1 +full:- +full:5
3 …tion. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro…
13 "Counter": "Fixed counter 1",
18 "CounterHTOff": "Fixed counter 1"
21 "Counter": "Fixed counter 1",
23 "AnyThread": "1",
27 "CounterHTOff": "Fixed counter 1"
30 …1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counte…
39 …-on-Store blocking code preventing store forwarding. This includes cases when:a. preceding store c…
41 "Counter": "0,1,2,3",
46 "CounterHTOff": "0,1,2,3,4,5,6,7"
51 "Counter": "0,1,2,3",
56 "CounterHTOff": "0,1,2,3,4,5,6,7"
61 "Counter": "0,1,2,3",
66 "CounterHTOff": "0,1,2,3,4,5,6,7"
71 "Counter": "0,1,2,3",
76 "CounterHTOff": "0,1,2,3,4,5,6,7"
80 "Counter": "0,1,2,3",
82 "AnyThread": "1",
86 "CounterHTOff": "0,1,2,3,4,5,6,7"
90 "Counter": "0,1,2,3",
94 …"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path …
95 "CounterHTOff": "0,1,2,3,4,5,6,7"
100 "Counter": "0,1,2,3",
105 "CounterHTOff": "0,1,2,3,4,5,6,7"
110 "Invert": "1",
111 "Counter": "0,1,2,3",
116 "CounterMask": "1",
117 "CounterHTOff": "0,1,2,3,4,5,6,7"
120 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio…
122 "Counter": "0,1,2,3",
126 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
127 "CounterHTOff": "0,1,2,3,4,5,6,7"
131 "Counter": "0,1,2,3",
136 "CounterHTOff": "0,1,2,3,4,5,6,7"
140 "Counter": "0,1,2,3",
144 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
145 "CounterMask": "1",
146 "CounterHTOff": "0,1,2,3,4,5,6,7"
151 "Counter": "0,1,2,3",
156 "CounterHTOff": "0,1,2,3,4,5,6,7"
160 "Counter": "0,1,2,3",
162 "AnyThread": "1",
166 "CounterHTOff": "0,1,2,3,4,5,6,7"
169 …"PublicDescription": "Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or …
171 "Counter": "0,1,2,3",
173 "EdgeDetect": "1",
176 "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
177 "CounterMask": "1",
178 "CounterHTOff": "0,1,2,3,4,5,6,7"
182 "Counter": "0,1,2,3",
187 "CounterHTOff": "0,1,2,3,4,5,6,7"
191 "Counter": "0,1,2,3",
193 "AnyThread": "1",
197 "CounterHTOff": "0,1,2,3,4,5,6,7"
201 "Counter": "0,1,2,3",
206 "CounterHTOff": "0,1,2,3,4,5,6,7"
210 "Counter": "0,1,2,3",
212 "AnyThread": "1",
216 "CounterHTOff": "0,1,2,3,4,5,6,7"
220 "Counter": "0,1,2,3",
225 "CounterHTOff": "0,1,2,3,4,5,6,7"
229 "Counter": "0,1,2,3",
234 "CounterHTOff": "0,1,2,3,4,5,6,7"
237 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
239 "Counter": "0,1,2,3",
244 "CounterHTOff": "0,1,2,3,4,5,6,7"
249 "Counter": "0,1,2,3",
254 "CounterHTOff": "0,1,2,3,4,5,6,7"
257 …ing which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thre…
259 "Counter": "0,1,2,3",
264 "CounterHTOff": "0,1,2,3,4,5,6,7"
267 …eservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound iss…
269 "Invert": "1",
270 "Counter": "0,1,2,3",
272 "EdgeDetect": "1",
276 "CounterMask": "1",
277 "CounterHTOff": "0,1,2,3,4,5,6,7"
280 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
282 "Counter": "0,1,2,3",
287 "CounterHTOff": "0,1,2,3,4,5,6,7"
290 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
292 "Counter": "0,1,2,3",
297 "CounterHTOff": "0,1,2,3,4,5,6,7"
300 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
302 "Counter": "0,1,2,3",
306 "BriefDescription": "Cycles per thread when uops are executed in port 1",
307 "CounterHTOff": "0,1,2,3,4,5,6,7"
310 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
312 "Counter": "0,1,2,3",
317 "CounterHTOff": "0,1,2,3,4,5,6,7"
320 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
322 "Counter": "0,1,2,3",
327 "CounterHTOff": "0,1,2,3,4,5,6,7"
330 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
332 "Counter": "0,1,2,3",
337 "CounterHTOff": "0,1,2,3,4,5,6,7"
340 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
342 "Counter": "0,1,2,3",
346 "BriefDescription": "Cycles per thread when uops are executed in port 5",
347 "CounterHTOff": "0,1,2,3,4,5,6,7"
350 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
352 "Counter": "0,1,2,3",
357 "CounterHTOff": "0,1,2,3,4,5,6,7"
360 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
362 "Counter": "0,1,2,3",
367 "CounterHTOff": "0,1,2,3,4,5,6,7"
370 "PublicDescription": "Counts resource-related stall cycles.",
372 "Counter": "0,1,2,3",
376 "BriefDescription": "Resource-related stall cycles",
377 "CounterHTOff": "0,1,2,3,4,5,6,7"
380 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
382 "Counter": "0,1,2,3",
387 "CounterHTOff": "0,1,2,3,4,5,6,7"
391 "Counter": "0,1,2,3",
396 "CounterMask": "1",
397 "CounterHTOff": "0,1,2,3,4,5,6,7"
401 "Counter": "0,1,2,3",
407 "CounterHTOff": "0,1,2,3,4,5,6,7"
411 "Counter": "0,1,2,3",
416 "CounterMask": "5",
417 "CounterHTOff": "0,1,2,3,4,5,6,7"
421 "Counter": "0,1,2,3",
427 "CounterHTOff": "0,1,2,3,4,5,6,7"
431 "Counter": "0,1,2,3",
437 "CounterHTOff": "0,1,2,3,4,5,6,7"
441 "Counter": "0,1,2,3",
447 "CounterHTOff": "0,1,2,3,4,5,6,7"
451 "Counter": "0,1,2,3",
457 "CounterHTOff": "0,1,2,3"
462 "Counter": "0,1,2,3",
467 "CounterHTOff": "0,1,2,3,4,5,6,7"
470 …"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Re…
472 "Counter": "0,1,2,3",
474 "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
476 …"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was no…
477 "CounterHTOff": "0,1,2,3,4,5,6,7"
482 "Counter": "0,1,2,3",
487 "CounterHTOff": "0,1,2,3,4,5,6,7"
492 "Counter": "0,1,2,3",
497 "CounterHTOff": "0,1,2,3,4,5,6,7"
502 "Counter": "0,1,2,3",
507 "CounterHTOff": "0,1,2,3,4,5,6,7"
511 "Counter": "0,1,2,3",
516 "CounterHTOff": "0,1,2,3,4,5,6,7"
519 … "PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
521 "Counter": "0,1,2,3",
526 "CounterHTOff": "0,1,2,3,4,5,6,7"
529 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
531 "Counter": "0,1,2,3",
536 "CounterMask": "1",
537 "CounterHTOff": "0,1,2,3,4,5,6,7"
540 …"PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector…
542 "Counter": "0,1,2,3",
548 "CounterHTOff": "0,1,2,3,4,5,6,7"
551 "PublicDescription": "Number of uops to be executed per-thread each cycle.",
553 "Counter": "0,1,2,3",
557 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
558 "CounterHTOff": "0,1,2,3,4,5,6,7"
563 "Invert": "1",
564 "Counter": "0,1,2,3",
569 "CounterMask": "1",
570 "CounterHTOff": "0,1,2,3,4,5,6,7"
573 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
575 "Counter": "0,1,2,3",
579 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
580 "CounterMask": "1",
581 "CounterHTOff": "0,1,2,3,4,5,6,7"
584 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
586 "Counter": "0,1,2,3",
590 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
592 "CounterHTOff": "0,1,2,3,4,5,6,7"
595 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
597 "Counter": "0,1,2,3",
601 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
603 "CounterHTOff": "0,1,2,3,4,5,6,7"
606 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
608 "Counter": "0,1,2,3",
612 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
614 "CounterHTOff": "0,1,2,3,4,5,6,7"
619 "Counter": "0,1,2,3",
624 "CounterHTOff": "0,1,2,3,4,5,6,7"
628 "Counter": "0,1,2,3",
632 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
633 "CounterMask": "1",
634 "CounterHTOff": "0,1,2,3,4,5,6,7"
638 "Counter": "0,1,2,3",
642 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
644 "CounterHTOff": "0,1,2,3,4,5,6,7"
648 "Counter": "0,1,2,3",
652 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
654 "CounterHTOff": "0,1,2,3,4,5,6,7"
658 "Counter": "0,1,2,3",
662 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
664 "CounterHTOff": "0,1,2,3,4,5,6,7"
668 "Invert": "1",
669 "Counter": "0,1,2,3",
673 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
674 "CounterMask": "1",
675 "CounterHTOff": "0,1,2,3,4,5,6,7"
680 "Counter": "0,1,2,3",
685 "CounterHTOff": "0,1,2,3,4,5,6,7"
688 …n": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions in…
690 "Counter": "0,1,2,3",
695 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
696 "CounterHTOff": "0,1,2,3,4,5,6,7"
702 "Counter": "1",
708 "CounterHTOff": "1"
714 "Invert": "1",
726 "Counter": "0,1,2,3",
730 …"BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Exa…
731 "CounterHTOff": "0,1,2,3,4,5,6,7"
736 "Counter": "0,1,2,3",
741 "CounterHTOff": "0,1,2,3,4,5,6,7"
746 "Invert": "1",
747 "Counter": "0,1,2,3",
752 "CounterMask": "1",
753 "CounterHTOff": "0,1,2,3,4,5,6,7"
758 "Invert": "1",
759 "Counter": "0,1,2,3",
765 "CounterHTOff": "0,1,2,3,4,5,6,7"
770 "Counter": "0,1,2,3",
772 "EdgeDetect": "1",
776 "CounterMask": "1",
777 "CounterHTOff": "0,1,2,3,4,5,6,7"
780 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
782 "Counter": "0,1,2,3",
786 "BriefDescription": "Self-modifying code (SMC) detected.",
787 "CounterHTOff": "0,1,2,3,4,5,6,7"
792 "Counter": "0,1,2,3",
798 "CounterHTOff": "0,1,2,3,4,5,6,7"
801 "PEBS": "1",
804 "Counter": "0,1,2,3",
810 "CounterHTOff": "0,1,2,3,4,5,6,7"
813 "PEBS": "1",
816 "Counter": "0,1,2,3",
822 "CounterHTOff": "0,1,2,3,4,5,6,7"
828 "Counter": "0,1,2,3",
834 "CounterHTOff": "0,1,2,3"
837 "PEBS": "1",
840 "Counter": "0,1,2,3",
846 "CounterHTOff": "0,1,2,3,4,5,6,7"
849 "PEBS": "1",
852 "Counter": "0,1,2,3",
858 "CounterHTOff": "0,1,2,3,4,5,6,7"
861 "PEBS": "1",
864 "Counter": "0,1,2,3",
870 "CounterHTOff": "0,1,2,3,4,5,6,7"
873 "PEBS": "1",
876 "Counter": "0,1,2,3",
882 "CounterHTOff": "0,1,2,3,4,5,6,7"
887 "Counter": "0,1,2,3",
892 "CounterHTOff": "0,1,2,3,4,5,6,7"
895 "PEBS": "1",
898 "Counter": "0,1,2,3",
903 "CounterHTOff": "0,1,2,3,4,5,6,7"
906 "PEBS": "1",
909 "Counter": "0,1,2,3",
914 "CounterHTOff": "0,1,2,3,4,5,6,7"
920 "Counter": "0,1,2,3",
925 "CounterHTOff": "0,1,2,3"
928 "PEBS": "1",
931 "Counter": "0,1,2,3",
936 "CounterHTOff": "0,1,2,3,4,5,6,7"
941 "Counter": "0,1,2,3",
946 "CounterHTOff": "0,1,2,3,4,5,6,7"
950 "Counter": "0,1,2,3",
955 "CounterHTOff": "0,1,2,3,4,5,6,7"
958 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
960 "Counter": "0,1,2,3",
965 "CounterHTOff": "0,1,2,3,4,5,6,7"