Lines Matching +full:0 +full:- +full:3
3 …tion. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro…
4 "Counter": "Fixed counter 0",
5 "UMask": "0x1",
9 "CounterHTOff": "Fixed counter 0"
14 "UMask": "0x2",
22 "UMask": "0x2",
32 "UMask": "0x3",
39 …-on-Store blocking code preventing store forwarding. This includes cases when:a. preceding store c…
40 "EventCode": "0x03",
41 "Counter": "0,1,2,3",
42 "UMask": "0x2",
46 "CounterHTOff": "0,1,2,3,4,5,6,7"
50 "EventCode": "0x03",
51 "Counter": "0,1,2,3",
52 "UMask": "0x8",
56 "CounterHTOff": "0,1,2,3,4,5,6,7"
60 "EventCode": "0x07",
61 "Counter": "0,1,2,3",
62 "UMask": "0x1",
66 "CounterHTOff": "0,1,2,3,4,5,6,7"
70 "EventCode": "0x0D",
71 "Counter": "0,1,2,3",
72 "UMask": "0x1",
76 "CounterHTOff": "0,1,2,3,4,5,6,7"
79 "EventCode": "0x0D",
80 "Counter": "0,1,2,3",
81 "UMask": "0x1",
86 "CounterHTOff": "0,1,2,3,4,5,6,7"
89 "EventCode": "0x0D",
90 "Counter": "0,1,2,3",
91 "UMask": "0x80",
94 …"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path …
95 "CounterHTOff": "0,1,2,3,4,5,6,7"
99 "EventCode": "0x0E",
100 "Counter": "0,1,2,3",
101 "UMask": "0x1",
105 "CounterHTOff": "0,1,2,3,4,5,6,7"
109 "EventCode": "0x0E",
111 "Counter": "0,1,2,3",
112 "UMask": "0x1",
117 "CounterHTOff": "0,1,2,3,4,5,6,7"
120 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio…
121 "EventCode": "0x0E",
122 "Counter": "0,1,2,3",
123 "UMask": "0x2",
126 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
127 "CounterHTOff": "0,1,2,3,4,5,6,7"
130 "EventCode": "0x0E",
131 "Counter": "0,1,2,3",
132 "UMask": "0x20",
135 …w LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sour…
136 "CounterHTOff": "0,1,2,3,4,5,6,7"
139 "EventCode": "0x14",
140 "Counter": "0,1,2,3",
141 "UMask": "0x1",
144 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
146 "CounterHTOff": "0,1,2,3,4,5,6,7"
150 "EventCode": "0x3C",
151 "Counter": "0,1,2,3",
152 "UMask": "0x0",
156 "CounterHTOff": "0,1,2,3,4,5,6,7"
159 "EventCode": "0x3C",
160 "Counter": "0,1,2,3",
161 "UMask": "0x0",
166 "CounterHTOff": "0,1,2,3,4,5,6,7"
169 …Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel).",
170 "EventCode": "0x3C",
171 "Counter": "0,1,2,3",
172 "UMask": "0x0",
176 "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
178 "CounterHTOff": "0,1,2,3,4,5,6,7"
181 "EventCode": "0x3C",
182 "Counter": "0,1,2,3",
183 "UMask": "0x1",
187 "CounterHTOff": "0,1,2,3,4,5,6,7"
190 "EventCode": "0x3C",
191 "Counter": "0,1,2,3",
192 "UMask": "0x1",
197 "CounterHTOff": "0,1,2,3,4,5,6,7"
200 "EventCode": "0x3C",
201 "Counter": "0,1,2,3",
202 "UMask": "0x1",
206 "CounterHTOff": "0,1,2,3,4,5,6,7"
209 "EventCode": "0x3C",
210 "Counter": "0,1,2,3",
211 "UMask": "0x1",
216 "CounterHTOff": "0,1,2,3,4,5,6,7"
219 "EventCode": "0x3C",
220 "Counter": "0,1,2,3",
221 "UMask": "0x2",
225 "CounterHTOff": "0,1,2,3,4,5,6,7"
228 "EventCode": "0x3C",
229 "Counter": "0,1,2,3",
230 "UMask": "0x2",
234 "CounterHTOff": "0,1,2,3,4,5,6,7"
237 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
238 "EventCode": "0x4C",
239 "Counter": "0,1,2,3",
240 "UMask": "0x1",
244 "CounterHTOff": "0,1,2,3,4,5,6,7"
248 "EventCode": "0x59",
249 "Counter": "0,1,2,3",
250 "UMask": "0x1",
254 "CounterHTOff": "0,1,2,3,4,5,6,7"
257 …vation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. …
258 "EventCode": "0x5E",
259 "Counter": "0,1,2,3",
260 "UMask": "0x1",
264 "CounterHTOff": "0,1,2,3,4,5,6,7"
267 …eservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound iss…
268 "EventCode": "0x5E",
270 "Counter": "0,1,2,3",
271 "UMask": "0x1",
277 "CounterHTOff": "0,1,2,3,4,5,6,7"
280 …0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the num…
281 "EventCode": "0x87",
282 "Counter": "0,1,2,3",
283 "UMask": "0x1",
287 "CounterHTOff": "0,1,2,3,4,5,6,7"
290 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
291 "EventCode": "0xA1",
292 "Counter": "0,1,2,3",
293 "UMask": "0x1",
296 "BriefDescription": "Cycles per thread when uops are executed in port 0",
297 "CounterHTOff": "0,1,2,3,4,5,6,7"
300 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
301 "EventCode": "0xA1",
302 "Counter": "0,1,2,3",
303 "UMask": "0x2",
307 "CounterHTOff": "0,1,2,3,4,5,6,7"
310 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
311 "EventCode": "0xA1",
312 "Counter": "0,1,2,3",
313 "UMask": "0x4",
317 "CounterHTOff": "0,1,2,3,4,5,6,7"
320 …": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the R…
321 "EventCode": "0xA1",
322 "Counter": "0,1,2,3",
323 "UMask": "0x8",
326 "BriefDescription": "Cycles per thread when uops are executed in port 3",
327 "CounterHTOff": "0,1,2,3,4,5,6,7"
330 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
331 "EventCode": "0xA1",
332 "Counter": "0,1,2,3",
333 "UMask": "0x10",
337 "CounterHTOff": "0,1,2,3,4,5,6,7"
340 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
341 "EventCode": "0xA1",
342 "Counter": "0,1,2,3",
343 "UMask": "0x20",
347 "CounterHTOff": "0,1,2,3,4,5,6,7"
350 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
351 "EventCode": "0xA1",
352 "Counter": "0,1,2,3",
353 "UMask": "0x40",
357 "CounterHTOff": "0,1,2,3,4,5,6,7"
360 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
361 "EventCode": "0xA1",
362 "Counter": "0,1,2,3",
363 "UMask": "0x80",
367 "CounterHTOff": "0,1,2,3,4,5,6,7"
370 "PublicDescription": "Counts resource-related stall cycles.",
371 "EventCode": "0xa2",
372 "Counter": "0,1,2,3",
373 "UMask": "0x1",
376 "BriefDescription": "Resource-related stall cycles",
377 "CounterHTOff": "0,1,2,3,4,5,6,7"
380 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
381 "EventCode": "0xA2",
382 "Counter": "0,1,2,3",
383 "UMask": "0x8",
387 "CounterHTOff": "0,1,2,3,4,5,6,7"
390 "EventCode": "0xA3",
391 "Counter": "0,1,2,3",
392 "UMask": "0x1",
397 "CounterHTOff": "0,1,2,3,4,5,6,7"
400 "EventCode": "0xA3",
401 "Counter": "0,1,2,3",
402 "UMask": "0x4",
407 "CounterHTOff": "0,1,2,3,4,5,6,7"
410 "EventCode": "0xA3",
411 "Counter": "0,1,2,3",
412 "UMask": "0x5",
417 "CounterHTOff": "0,1,2,3,4,5,6,7"
420 "EventCode": "0xA3",
421 "Counter": "0,1,2,3",
422 "UMask": "0x8",
427 "CounterHTOff": "0,1,2,3,4,5,6,7"
430 "EventCode": "0xA3",
431 "Counter": "0,1,2,3",
432 "UMask": "0xc",
437 "CounterHTOff": "0,1,2,3,4,5,6,7"
440 "EventCode": "0xA3",
441 "Counter": "0,1,2,3",
442 "UMask": "0x10",
447 "CounterHTOff": "0,1,2,3,4,5,6,7"
450 "EventCode": "0xA3",
451 "Counter": "0,1,2,3",
452 "UMask": "0x14",
457 "CounterHTOff": "0,1,2,3"
461 "EventCode": "0xA6",
462 "Counter": "0,1,2,3",
463 "UMask": "0x1",
467 "CounterHTOff": "0,1,2,3,4,5,6,7"
471 "EventCode": "0xA6",
472 "Counter": "0,1,2,3",
473 "UMask": "0x2",
477 "CounterHTOff": "0,1,2,3,4,5,6,7"
481 "EventCode": "0xA6",
482 "Counter": "0,1,2,3",
483 "UMask": "0x4",
487 "CounterHTOff": "0,1,2,3,4,5,6,7"
490 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
491 "EventCode": "0xA6",
492 "Counter": "0,1,2,3",
493 "UMask": "0x8",
494 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
496 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
497 "CounterHTOff": "0,1,2,3,4,5,6,7"
501 "EventCode": "0xA6",
502 "Counter": "0,1,2,3",
503 "UMask": "0x10",
507 "CounterHTOff": "0,1,2,3,4,5,6,7"
510 "EventCode": "0xA6",
511 "Counter": "0,1,2,3",
512 "UMask": "0x40",
516 "CounterHTOff": "0,1,2,3,4,5,6,7"
519 … "PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
520 "EventCode": "0xA8",
521 "Counter": "0,1,2,3",
522 "UMask": "0x1",
526 "CounterHTOff": "0,1,2,3,4,5,6,7"
529 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
530 "EventCode": "0xA8",
531 "Counter": "0,1,2,3",
532 "UMask": "0x1",
537 "CounterHTOff": "0,1,2,3,4,5,6,7"
540 …"PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector…
541 "EventCode": "0xA8",
542 "Counter": "0,1,2,3",
543 "UMask": "0x1",
548 "CounterHTOff": "0,1,2,3,4,5,6,7"
551 "PublicDescription": "Number of uops to be executed per-thread each cycle.",
552 "EventCode": "0xB1",
553 "Counter": "0,1,2,3",
554 "UMask": "0x1",
557 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
558 "CounterHTOff": "0,1,2,3,4,5,6,7"
562 "EventCode": "0xB1",
564 "Counter": "0,1,2,3",
565 "UMask": "0x1",
570 "CounterHTOff": "0,1,2,3,4,5,6,7"
573 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
574 "EventCode": "0xB1",
575 "Counter": "0,1,2,3",
576 "UMask": "0x1",
579 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
581 "CounterHTOff": "0,1,2,3,4,5,6,7"
584 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
585 "EventCode": "0xB1",
586 "Counter": "0,1,2,3",
587 "UMask": "0x1",
590 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
592 "CounterHTOff": "0,1,2,3,4,5,6,7"
595 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
596 "EventCode": "0xB1",
597 "Counter": "0,1,2,3",
598 "UMask": "0x1",
601 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
602 "CounterMask": "3",
603 "CounterHTOff": "0,1,2,3,4,5,6,7"
606 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
607 "EventCode": "0xB1",
608 "Counter": "0,1,2,3",
609 "UMask": "0x1",
612 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
614 "CounterHTOff": "0,1,2,3,4,5,6,7"
618 "EventCode": "0xB1",
619 "Counter": "0,1,2,3",
620 "UMask": "0x2",
624 "CounterHTOff": "0,1,2,3,4,5,6,7"
627 "EventCode": "0xB1",
628 "Counter": "0,1,2,3",
629 "UMask": "0x2",
632 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
634 "CounterHTOff": "0,1,2,3,4,5,6,7"
637 "EventCode": "0xB1",
638 "Counter": "0,1,2,3",
639 "UMask": "0x2",
642 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
644 "CounterHTOff": "0,1,2,3,4,5,6,7"
647 "EventCode": "0xB1",
648 "Counter": "0,1,2,3",
649 "UMask": "0x2",
652 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
653 "CounterMask": "3",
654 "CounterHTOff": "0,1,2,3,4,5,6,7"
657 "EventCode": "0xB1",
658 "Counter": "0,1,2,3",
659 "UMask": "0x2",
662 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
664 "CounterHTOff": "0,1,2,3,4,5,6,7"
667 "EventCode": "0xB1",
669 "Counter": "0,1,2,3",
670 "UMask": "0x2",
673 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
675 "CounterHTOff": "0,1,2,3,4,5,6,7"
679 "EventCode": "0xB1",
680 "Counter": "0,1,2,3",
681 "UMask": "0x10",
685 "CounterHTOff": "0,1,2,3,4,5,6,7"
688 …n": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions in…
689 "EventCode": "0xC0",
690 "Counter": "0,1,2,3",
691 "UMask": "0x0",
695 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
696 "CounterHTOff": "0,1,2,3,4,5,6,7"
701 "EventCode": "0xC0",
703 "UMask": "0x1",
713 "EventCode": "0xC0",
715 "Counter": "0,2,3",
716 "UMask": "0x1",
722 "CounterHTOff": "0,2,3"
725 "EventCode": "0xC1",
726 "Counter": "0,1,2,3",
727 "UMask": "0x3f",
730 …"BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Exa…
731 "CounterHTOff": "0,1,2,3,4,5,6,7"
735 "EventCode": "0xC2",
736 "Counter": "0,1,2,3",
737 "UMask": "0x2",
741 "CounterHTOff": "0,1,2,3,4,5,6,7"
745 "EventCode": "0xC2",
747 "Counter": "0,1,2,3",
748 "UMask": "0x2",
753 "CounterHTOff": "0,1,2,3,4,5,6,7"
757 "EventCode": "0xC2",
759 "Counter": "0,1,2,3",
760 "UMask": "0x2",
765 "CounterHTOff": "0,1,2,3,4,5,6,7"
769 "EventCode": "0xC3",
770 "Counter": "0,1,2,3",
771 "UMask": "0x1",
777 "CounterHTOff": "0,1,2,3,4,5,6,7"
780 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
781 "EventCode": "0xC3",
782 "Counter": "0,1,2,3",
783 "UMask": "0x4",
786 "BriefDescription": "Self-modifying code (SMC) detected.",
787 "CounterHTOff": "0,1,2,3,4,5,6,7"
791 "EventCode": "0xC4",
792 "Counter": "0,1,2,3",
793 "UMask": "0x0",
798 "CounterHTOff": "0,1,2,3,4,5,6,7"
803 "EventCode": "0xC4",
804 "Counter": "0,1,2,3",
805 "UMask": "0x1",
810 "CounterHTOff": "0,1,2,3,4,5,6,7"
815 "EventCode": "0xC4",
816 "Counter": "0,1,2,3",
817 "UMask": "0x2",
822 "CounterHTOff": "0,1,2,3,4,5,6,7"
827 "EventCode": "0xC4",
828 "Counter": "0,1,2,3",
829 "UMask": "0x4",
834 "CounterHTOff": "0,1,2,3"
839 "EventCode": "0xC4",
840 "Counter": "0,1,2,3",
841 "UMask": "0x8",
846 "CounterHTOff": "0,1,2,3,4,5,6,7"
851 "EventCode": "0xC4",
852 "Counter": "0,1,2,3",
853 "UMask": "0x10",
858 "CounterHTOff": "0,1,2,3,4,5,6,7"
863 "EventCode": "0xC4",
864 "Counter": "0,1,2,3",
865 "UMask": "0x20",
870 "CounterHTOff": "0,1,2,3,4,5,6,7"
875 "EventCode": "0xC4",
876 "Counter": "0,1,2,3",
877 "UMask": "0x40",
882 "CounterHTOff": "0,1,2,3,4,5,6,7"
886 "EventCode": "0xC5",
887 "Counter": "0,1,2,3",
888 "UMask": "0x0",
892 "CounterHTOff": "0,1,2,3,4,5,6,7"
897 "EventCode": "0xC5",
898 "Counter": "0,1,2,3",
899 "UMask": "0x1",
903 "CounterHTOff": "0,1,2,3,4,5,6,7"
908 "EventCode": "0xC5",
909 "Counter": "0,1,2,3",
910 "UMask": "0x2",
914 "CounterHTOff": "0,1,2,3,4,5,6,7"
919 "EventCode": "0xC5",
920 "Counter": "0,1,2,3",
921 "UMask": "0x4",
925 "CounterHTOff": "0,1,2,3"
930 "EventCode": "0xC5",
931 "Counter": "0,1,2,3",
932 "UMask": "0x20",
936 "CounterHTOff": "0,1,2,3,4,5,6,7"
940 "EventCode": "0xCC",
941 "Counter": "0,1,2,3",
942 "UMask": "0x20",
946 "CounterHTOff": "0,1,2,3,4,5,6,7"
949 "EventCode": "0xCC",
950 "Counter": "0,1,2,3",
951 "UMask": "0x40",
955 "CounterHTOff": "0,1,2,3,4,5,6,7"
958 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
959 "EventCode": "0xE6",
960 "Counter": "0,1,2,3",
961 "UMask": "0x1",
965 "CounterHTOff": "0,1,2,3,4,5,6,7"