Lines Matching +full:1 +full:- +full:based
3 "PEBS": "1",
4 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
6 "Counter": "0,1",
13 "PEBS": "1",
14 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
16 "Counter": "0,1",
23 "PEBS": "1",
24 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
26 "Counter": "0,1",
33 "PEBS": "1",
34 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
36 "Counter": "0,1",
43 "PEBS": "1",
44 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
46 "Counter": "0,1",
53 "PEBS": "1",
54 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
56 "Counter": "0,1",
63 "PEBS": "1",
64 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
66 "Counter": "0,1",
73 "PEBS": "1",
74 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
76 "Counter": "0,1",
83 "PEBS": "1",
84 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
86 "Counter": "0,1",
93 "PEBS": "1",
94 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
96 "Counter": "0,1",
103 "PEBS": "1",
104 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
106 "Counter": "0,1",
113 "PEBS": "1",
114 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
116 "Counter": "0,1",
123 "PEBS": "1",
124 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
126 "Counter": "0,1",
133 "PEBS": "1",
134 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
136 "Counter": "0,1",
143 "PEBS": "1",
144 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
146 "Counter": "0,1",
153 …"PublicDescription": "This event counts the number of micro-ops retired that were supplied from MS…
155 "Counter": "0,1",
159 "BriefDescription": "MSROM micro-ops retired"
162 …-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-op…
164 "Counter": "0,1",
168 "BriefDescription": "Micro-ops retired"
171 …ent counts the number of times that a program writes to a code section. Self-modifying code causes…
173 "Counter": "0,1",
177 "BriefDescription": "Self-Modifying Code detected"
182 "Counter": "0,1",
191 "Counter": "0,1",
200 "Counter": "0,1",
209 "Counter": "0,1",
217 "Counter": "0,1",
224 …-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-en…
226 "Counter": "0,1",
233 …": "The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide …
235 "Counter": "0,1",
242 …ropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion …
244 "Counter": "0,1",
248 …ropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion …
252 "Counter": "0,1",
259 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
261 "Counter": "0,1",
270 "Counter": "0,1",
277 … For instructions that consist of multiple micro-ops, this event counts exactly once, as the last …
278 "Counter": "Fixed counter 1",
303 "Counter": "0,1",
312 "Counter": "0,1",
321 "Counter": "0,1",
330 "Counter": "0,1",
339 "Counter": "0,1",
347 …ction. This unit predicts the target address not only based on the EIP of the branch but also base…
349 "Counter": "0,1",
351 "PEBScounters": "0,1",