Lines Matching +full:0 +full:- +full:3
5 "UMask": "0x3",
12 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
13 "Counter": "Fixed counter 0",
14 "UMask": "0x1",
18 "CounterHTOff": "Fixed counter 0"
23 "UMask": "0x2",
31 "UMask": "0x2",
39 "EventCode": "0x03",
40 "Counter": "0,1,2,3",
41 "UMask": "0x1",
45 "CounterHTOff": "0,1,2,3,4,5,6,7"
48 … See the table of not supported store forwards in the Intel\u00ae 64 and IA-32 Architectures Opti…
49 "EventCode": "0x03",
50 "Counter": "0,1,2,3",
51 "UMask": "0x2",
54 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
55 "CounterHTOff": "0,1,2,3,4,5,6,7"
58 "EventCode": "0x03",
59 "Counter": "0,1,2,3",
60 "UMask": "0x8",
64 "CounterHTOff": "0,1,2,3,4,5,6,7"
67 "EventCode": "0x03",
68 "Counter": "0,1,2,3",
69 "UMask": "0x10",
72 …"BriefDescription": "Number of cases where any load ends up with a valid block-code written to the…
73 "CounterHTOff": "0,1,2,3,4,5,6,7"
77 "EventCode": "0x07",
78 "Counter": "0,1,2,3",
79 "UMask": "0x1",
83 "CounterHTOff": "0,1,2,3,4,5,6,7"
86 "EventCode": "0x07",
87 "Counter": "0,1,2,3",
88 "UMask": "0x8",
92 "CounterHTOff": "0,1,2,3,4,5,6,7"
95 "EventCode": "0x0D",
96 "Counter": "0,1,2,3",
97 "UMask": "0x3",
102 "CounterHTOff": "0,1,2,3,4,5,6,7"
105 "EventCode": "0x0D",
106 "Counter": "0,1,2,3",
107 "UMask": "0x3",
113 "CounterHTOff": "0,1,2,3,4,5,6,7"
116 "EventCode": "0x0D",
117 "Counter": "0,1,2,3",
118 "UMask": "0x3",
124 "CounterHTOff": "0,1,2,3,4,5,6,7"
127 "EventCode": "0x0D",
128 "Counter": "0,1,2,3",
129 "UMask": "0x40",
133 "CounterHTOff": "0,1,2,3,4,5,6,7"
136 …": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
137 "EventCode": "0x0E",
138 "Counter": "0,1,2,3",
139 "UMask": "0x1",
143 "CounterHTOff": "0,1,2,3,4,5,6,7"
146 "EventCode": "0x0E",
148 "Counter": "0,1,2,3",
149 "UMask": "0x1",
154 "CounterHTOff": "0,1,2,3"
157 "EventCode": "0x0E",
159 "Counter": "0,1,2,3",
160 "UMask": "0x1",
166 "CounterHTOff": "0,1,2,3"
169 "EventCode": "0x14",
170 "Counter": "0,1,2,3",
171 "UMask": "0x1",
175 "CounterHTOff": "0,1,2,3,4,5,6,7"
179 "EventCode": "0x14",
180 "Counter": "0,1,2,3",
181 "UMask": "0x1",
187 "CounterHTOff": "0,1,2,3,4,5,6,7"
190 "EventCode": "0x3C",
191 "Counter": "0,1,2,3",
192 "UMask": "0x0",
196 "CounterHTOff": "0,1,2,3,4,5,6,7"
199 "EventCode": "0x3C",
200 "Counter": "0,1,2,3",
201 "UMask": "0x0",
206 "CounterHTOff": "0,1,2,3,4,5,6,7"
209 "EventCode": "0x3C",
210 "Counter": "0,1,2,3",
211 "UMask": "0x1",
215 "CounterHTOff": "0,1,2,3,4,5,6,7"
218 "EventCode": "0x3C",
219 "Counter": "0,1,2,3",
220 "UMask": "0x1",
225 "CounterHTOff": "0,1,2,3,4,5,6,7"
229 "EventCode": "0x3C",
230 "Counter": "0,1,2,3",
231 "UMask": "0x1",
235 "CounterHTOff": "0,1,2,3,4,5,6,7"
238 "EventCode": "0x3C",
239 "Counter": "0,1,2,3",
240 "UMask": "0x1",
245 "CounterHTOff": "0,1,2,3,4,5,6,7"
248 "EventCode": "0x3C",
249 "Counter": "0,1,2,3",
250 "UMask": "0x2",
254 "CounterHTOff": "0,1,2,3"
257 "EventCode": "0x3C",
258 "Counter": "0,1,2,3",
259 "UMask": "0x2",
263 "CounterHTOff": "0,1,2,3,4,5,6,7"
266 "EventCode": "0x4C",
267 "Counter": "0,1,2,3",
268 "UMask": "0x1",
271 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
272 "CounterHTOff": "0,1,2,3,4,5,6,7"
275 "EventCode": "0x4C",
276 "Counter": "0,1,2,3",
277 "UMask": "0x2",
280 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
281 "CounterHTOff": "0,1,2,3,4,5,6,7"
284 "EventCode": "0x59",
285 "Counter": "0,1,2,3",
286 "UMask": "0x20",
289 "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
290 "CounterHTOff": "0,1,2,3,4,5,6,7"
293 …ing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more …
294 "EventCode": "0x59",
295 "Counter": "0,1,2,3",
296 "UMask": "0x20",
299 … "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
301 "CounterHTOff": "0,1,2,3,4,5,6,7"
304 …here base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel\u00ae 64 an…
305 "EventCode": "0x59",
306 "Counter": "0,1,2,3",
307 "UMask": "0x40",
311 "CounterHTOff": "0,1,2,3,4,5,6,7"
314 "EventCode": "0x59",
315 "Counter": "0,1,2,3",
316 "UMask": "0x80",
320 "CounterHTOff": "0,1,2,3,4,5,6,7"
323 "EventCode": "0x5B",
324 "Counter": "0,1,2,3",
325 "UMask": "0xc",
329 "CounterHTOff": "0,1,2,3,4,5,6,7"
332 "EventCode": "0x5B",
333 "Counter": "0,1,2,3",
334 "UMask": "0xf",
338 "CounterHTOff": "0,1,2,3,4,5,6,7"
341 "EventCode": "0x5B",
342 "Counter": "0,1,2,3",
343 "UMask": "0x40",
347 "CounterHTOff": "0,1,2,3,4,5,6,7"
350 "EventCode": "0x5B",
351 "Counter": "0,1,2,3",
352 "UMask": "0x4f",
356 "CounterHTOff": "0,1,2,3,4,5,6,7"
359 "EventCode": "0x5E",
360 "Counter": "0,1,2,3",
361 "UMask": "0x1",
365 "CounterHTOff": "0,1,2,3,4,5,6,7"
368 "EventCode": "0x5E",
370 "Counter": "0,1,2,3",
371 "UMask": "0x1",
377 "CounterHTOff": "0,1,2,3,4,5,6,7"
380 "EventCode": "0x87",
381 "Counter": "0,1,2,3",
382 "UMask": "0x1",
386 "CounterHTOff": "0,1,2,3,4,5,6,7"
389 "EventCode": "0x87",
390 "Counter": "0,1,2,3",
391 "UMask": "0x4",
395 "CounterHTOff": "0,1,2,3,4,5,6,7"
398 "EventCode": "0x88",
399 "Counter": "0,1,2,3",
400 "UMask": "0x41",
403 "BriefDescription": "Not taken macro-conditional branches.",
404 "CounterHTOff": "0,1,2,3,4,5,6,7"
407 "EventCode": "0x88",
408 "Counter": "0,1,2,3",
409 "UMask": "0x81",
412 "BriefDescription": "Taken speculative and retired macro-conditional branches.",
413 "CounterHTOff": "0,1,2,3,4,5,6,7"
416 "EventCode": "0x88",
417 "Counter": "0,1,2,3",
418 "UMask": "0x82",
421 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
422 "CounterHTOff": "0,1,2,3,4,5,6,7"
425 "EventCode": "0x88",
426 "Counter": "0,1,2,3",
427 "UMask": "0x84",
431 "CounterHTOff": "0,1,2,3,4,5,6,7"
434 "EventCode": "0x88",
435 "Counter": "0,1,2,3",
436 "UMask": "0x88",
440 "CounterHTOff": "0,1,2,3,4,5,6,7"
443 "EventCode": "0x88",
444 "Counter": "0,1,2,3",
445 "UMask": "0x90",
449 "CounterHTOff": "0,1,2,3,4,5,6,7"
452 "EventCode": "0x88",
453 "Counter": "0,1,2,3",
454 "UMask": "0xa0",
458 "CounterHTOff": "0,1,2,3,4,5,6,7"
461 "EventCode": "0x88",
462 "Counter": "0,1,2,3",
463 "UMask": "0xc1",
466 "BriefDescription": "Speculative and retired macro-conditional branches.",
467 "CounterHTOff": "0,1,2,3,4,5,6,7"
470 "EventCode": "0x88",
471 "Counter": "0,1,2,3",
472 "UMask": "0xc2",
475 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
476 "CounterHTOff": "0,1,2,3,4,5,6,7"
479 "EventCode": "0x88",
480 "Counter": "0,1,2,3",
481 "UMask": "0xc4",
485 "CounterHTOff": "0,1,2,3,4,5,6,7"
488 "EventCode": "0x88",
489 "Counter": "0,1,2,3",
490 "UMask": "0xc8",
494 "CounterHTOff": "0,1,2,3,4,5,6,7"
497 "EventCode": "0x88",
498 "Counter": "0,1,2,3",
499 "UMask": "0xd0",
503 "CounterHTOff": "0,1,2,3,4,5,6,7"
506 "EventCode": "0x88",
507 "Counter": "0,1,2,3",
508 "UMask": "0xff",
512 "CounterHTOff": "0,1,2,3,4,5,6,7"
515 "EventCode": "0x89",
516 "Counter": "0,1,2,3",
517 "UMask": "0x41",
521 "CounterHTOff": "0,1,2,3,4,5,6,7"
524 "EventCode": "0x89",
525 "Counter": "0,1,2,3",
526 "UMask": "0x81",
530 "CounterHTOff": "0,1,2,3,4,5,6,7"
533 "EventCode": "0x89",
534 "Counter": "0,1,2,3",
535 "UMask": "0x84",
539 "CounterHTOff": "0,1,2,3,4,5,6,7"
542 "EventCode": "0x89",
543 "Counter": "0,1,2,3",
544 "UMask": "0x88",
548 "CounterHTOff": "0,1,2,3,4,5,6,7"
551 "EventCode": "0x89",
552 "Counter": "0,1,2,3",
553 "UMask": "0x90",
557 "CounterHTOff": "0,1,2,3,4,5,6,7"
560 "EventCode": "0x89",
561 "Counter": "0,1,2,3",
562 "UMask": "0xa0",
566 "CounterHTOff": "0,1,2,3,4,5,6,7"
569 "EventCode": "0x89",
570 "Counter": "0,1,2,3",
571 "UMask": "0xc1",
575 "CounterHTOff": "0,1,2,3,4,5,6,7"
578 "EventCode": "0x89",
579 "Counter": "0,1,2,3",
580 "UMask": "0xc4",
584 "CounterHTOff": "0,1,2,3,4,5,6,7"
587 "EventCode": "0x89",
588 "Counter": "0,1,2,3",
589 "UMask": "0xd0",
593 "CounterHTOff": "0,1,2,3,4,5,6,7"
596 "EventCode": "0x89",
597 "Counter": "0,1,2,3",
598 "UMask": "0xff",
602 "CounterHTOff": "0,1,2,3,4,5,6,7"
605 "EventCode": "0xA1",
606 "Counter": "0,1,2,3",
607 "UMask": "0x1",
610 "BriefDescription": "Cycles per thread when uops are dispatched to port 0.",
611 "CounterHTOff": "0,1,2,3,4,5,6,7"
614 "EventCode": "0xA1",
615 "Counter": "0,1,2,3",
616 "UMask": "0x1",
620 "BriefDescription": "Cycles per core when uops are dispatched to port 0.",
621 "CounterHTOff": "0,1,2,3,4,5,6,7"
624 "EventCode": "0xA1",
625 "Counter": "0,1,2,3",
626 "UMask": "0x2",
630 "CounterHTOff": "0,1,2,3,4,5,6,7"
633 "EventCode": "0xA1",
634 "Counter": "0,1,2,3",
635 "UMask": "0x2",
640 "CounterHTOff": "0,1,2,3,4,5,6,7"
643 "EventCode": "0xA1",
644 "Counter": "0,1,2,3",
645 "UMask": "0xc",
649 "CounterHTOff": "0,1,2,3,4,5,6,7"
652 "EventCode": "0xA1",
653 "Counter": "0,1,2,3",
654 "UMask": "0xc",
659 "CounterHTOff": "0,1,2,3,4,5,6,7"
662 "EventCode": "0xA1",
663 "Counter": "0,1,2,3",
664 "UMask": "0x30",
667 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.",
668 "CounterHTOff": "0,1,2,3,4,5,6,7"
671 "EventCode": "0xA1",
672 "Counter": "0,1,2,3",
673 "UMask": "0x30",
677 "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
678 "CounterHTOff": "0,1,2,3,4,5,6,7"
681 "EventCode": "0xA1",
682 "Counter": "0,1,2,3",
683 "UMask": "0x40",
687 "CounterHTOff": "0,1,2,3,4,5,6,7"
690 "EventCode": "0xA1",
691 "Counter": "0,1,2,3",
692 "UMask": "0x40",
697 "CounterHTOff": "0,1,2,3,4,5,6,7"
700 "EventCode": "0xA1",
701 "Counter": "0,1,2,3",
702 "UMask": "0x80",
706 "CounterHTOff": "0,1,2,3,4,5,6,7"
709 "EventCode": "0xA1",
710 "Counter": "0,1,2,3",
711 "UMask": "0x80",
716 "CounterHTOff": "0,1,2,3,4,5,6,7"
719 "EventCode": "0xA2",
720 "Counter": "0,1,2,3",
721 "UMask": "0x1",
724 "BriefDescription": "Resource-related stall cycles.",
725 "CounterHTOff": "0,1,2,3,4,5,6,7"
728 "EventCode": "0xA2",
729 "Counter": "0,1,2,3",
730 "UMask": "0x2",
734 "CounterHTOff": "0,1,2,3,4,5,6,7"
737 "EventCode": "0xA2",
738 "Counter": "0,1,2,3",
739 "UMask": "0x4",
743 "CounterHTOff": "0,1,2,3,4,5,6,7"
746 "EventCode": "0xA2",
747 "Counter": "0,1,2,3",
748 "UMask": "0x8",
752 "CounterHTOff": "0,1,2,3,4,5,6,7"
755 "EventCode": "0xA2",
756 "Counter": "0,1,2,3",
757 "UMask": "0xa",
761 "CounterHTOff": "0,1,2,3,4,5,6,7"
764 "EventCode": "0xA2",
765 "Counter": "0,1,2,3",
766 "UMask": "0xe",
770 "CounterHTOff": "0,1,2,3,4,5,6,7"
773 "EventCode": "0xA2",
774 "Counter": "0,1,2,3",
775 "UMask": "0x10",
778 "BriefDescription": "Cycles stalled due to re-order buffer full.",
779 "CounterHTOff": "0,1,2,3,4,5,6,7"
782 "EventCode": "0xA2",
783 "Counter": "0,1,2,3",
784 "UMask": "0xf0",
788 "CounterHTOff": "0,1,2,3,4,5,6,7"
791 "EventCode": "0xA3",
792 "Counter": "0,1,2,3",
793 "UMask": "0x1",
796 …-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load…
798 "CounterHTOff": "0,1,2,3,4,5,6,7"
801 "EventCode": "0xA3",
803 "UMask": "0x2",
806 …miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1…
811 "EventCode": "0xA3",
812 "Counter": "0,1,2,3",
813 "UMask": "0x4",
818 "CounterHTOff": "0,1,2,3"
821 "EventCode": "0xA3",
822 "Counter": "0,1,2,3",
823 "UMask": "0x5",
826 …-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry…
828 "CounterHTOff": "0,1,2,3"
831 "EventCode": "0xA3",
833 "UMask": "0x6",
836 …-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and c…
841 "EventCode": "0xA8",
842 "Counter": "0,1,2,3",
843 "UMask": "0x1",
847 "CounterHTOff": "0,1,2,3,4,5,6,7"
850 "EventCode": "0xA8",
851 "Counter": "0,1,2,3",
852 "UMask": "0x1",
857 "CounterHTOff": "0,1,2,3,4,5,6,7"
860 "EventCode": "0xA8",
861 "Counter": "0,1,2,3",
862 "UMask": "0x1",
867 "CounterHTOff": "0,1,2,3,4,5,6,7"
870 "EventCode": "0xB1",
871 "Counter": "0,1,2,3",
872 "UMask": "0x1",
876 "CounterHTOff": "0,1,2,3,4,5,6,7"
879 "EventCode": "0xB1",
880 "Counter": "0,1,2,3",
881 "UMask": "0x2",
885 "CounterHTOff": "0,1,2,3,4,5,6,7"
888 "EventCode": "0xB1",
889 "Counter": "0,1,2,3",
890 "UMask": "0x2",
893 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
895 "CounterHTOff": "0,1,2,3,4,5,6,7"
898 "EventCode": "0xB1",
899 "Counter": "0,1,2,3",
900 "UMask": "0x2",
903 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
905 "CounterHTOff": "0,1,2,3,4,5,6,7"
908 "EventCode": "0xB1",
909 "Counter": "0,1,2,3",
910 "UMask": "0x2",
913 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
914 "CounterMask": "3",
915 "CounterHTOff": "0,1,2,3,4,5,6,7"
918 "EventCode": "0xB1",
919 "Counter": "0,1,2,3",
920 "UMask": "0x2",
923 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
925 "CounterHTOff": "0,1,2,3,4,5,6,7"
928 "EventCode": "0xB1",
930 "Counter": "0,1,2,3",
931 "UMask": "0x2",
934 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
935 "CounterHTOff": "0,1,2,3,4,5,6,7"
938 "EventCode": "0xB6",
939 "Counter": "0,1,2,3",
940 "UMask": "0x1",
943 …ressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specifi…
944 "CounterHTOff": "0,1,2,3,4,5,6,7"
947 "EventCode": "0xC0",
948 "Counter": "0,1,2,3",
949 "UMask": "0x0",
952 … "BriefDescription": "Number of instructions retired. General Counter - architectural event.",
953 "CounterHTOff": "0,1,2,3,4,5,6,7"
957 "EventCode": "0xC0",
959 "UMask": "0x1",
962 "BriefDescription": "Instructions retired. (Precise Event - PEBS).",
967 "EventCode": "0xC1",
968 "Counter": "0,1,2,3",
969 "UMask": "0x2",
973 "CounterHTOff": "0,1,2,3,4,5,6,7"
977 "PublicDescription": "This event counts the number of micro-ops retired. (Precise Event)",
978 "EventCode": "0xC2",
979 "Counter": "0,1,2,3",
980 "UMask": "0x1",
983 "BriefDescription": "Actually retired uops. (Precise Event - PEBS).",
984 "CounterHTOff": "0,1,2,3,4,5,6,7"
987 "EventCode": "0xC2",
989 "Counter": "0,1,2,3",
990 "UMask": "0x1",
995 "CounterHTOff": "0,1,2,3"
998 "EventCode": "0xC2",
1000 "Counter": "0,1,2,3",
1001 "UMask": "0x1",
1006 "CounterHTOff": "0,1,2,3"
1009 "EventCode": "0xC2",
1011 "Counter": "0,1,2,3",
1012 "UMask": "0x1",
1017 "CounterHTOff": "0,1,2,3"
1021 …- meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determini…
1022 "EventCode": "0xC2",
1023 "Counter": "0,1,2,3",
1024 "UMask": "0x2",
1027 "BriefDescription": "Retirement slots used. (Precise Event - PEBS).",
1028 "CounterHTOff": "0,1,2,3,4,5,6,7"
1031 "EventCode": "0xc3",
1032 "Counter": "0,1,2,3",
1033 "UMask": "0x1",
1039 "CounterHTOff": "0,1,2,3,4,5,6,7"
1042 …"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which …
1043 "EventCode": "0xC3",
1044 "Counter": "0,1,2,3",
1045 "UMask": "0x4",
1048 "BriefDescription": "Self-modifying code (SMC) detected.",
1049 "CounterHTOff": "0,1,2,3,4,5,6,7"
1052 …ription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to in…
1053 "EventCode": "0xC3",
1054 "Counter": "0,1,2,3",
1055 "UMask": "0x20",
1058 …el AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
1059 "CounterHTOff": "0,1,2,3,4,5,6,7"
1062 "EventCode": "0xC4",
1063 "Counter": "0,1,2,3",
1064 "UMask": "0x0",
1068 "CounterHTOff": "0,1,2,3,4,5,6,7"
1072 "EventCode": "0xC4",
1073 "Counter": "0,1,2,3",
1074 "UMask": "0x1",
1077 "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS).",
1078 "CounterHTOff": "0,1,2,3,4,5,6,7"
1082 "EventCode": "0xC4",
1083 "Counter": "0,1,2,3",
1084 "UMask": "0x2",
1087 … "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS).",
1088 "CounterHTOff": "0,1,2,3,4,5,6,7"
1092 "EventCode": "0xC4",
1093 "Counter": "0,1,2,3",
1094 "UMask": "0x2",
1097 …t and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).",
1098 "CounterHTOff": "0,1,2,3,4,5,6,7"
1102 "EventCode": "0xC4",
1103 "Counter": "0,1,2,3",
1104 "UMask": "0x4",
1107 "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
1108 "CounterHTOff": "0,1,2,3"
1112 "EventCode": "0xC4",
1113 "Counter": "0,1,2,3",
1114 "UMask": "0x8",
1117 "BriefDescription": "Return instructions retired. (Precise Event - PEBS).",
1118 "CounterHTOff": "0,1,2,3,4,5,6,7"
1121 "EventCode": "0xC4",
1122 "Counter": "0,1,2,3",
1123 "UMask": "0x10",
1127 "CounterHTOff": "0,1,2,3,4,5,6,7"
1131 "EventCode": "0xC4",
1132 "Counter": "0,1,2,3",
1133 "UMask": "0x20",
1136 "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS).",
1137 "CounterHTOff": "0,1,2,3,4,5,6,7"
1140 "EventCode": "0xC4",
1141 "Counter": "0,1,2,3",
1142 "UMask": "0x40",
1146 "CounterHTOff": "0,1,2,3,4,5,6,7"
1149 "EventCode": "0xC5",
1150 "Counter": "0,1,2,3",
1151 "UMask": "0x0",
1155 "CounterHTOff": "0,1,2,3,4,5,6,7"
1159 "EventCode": "0xC5",
1160 "Counter": "0,1,2,3",
1161 "UMask": "0x1",
1164 …"BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS).…
1165 "CounterHTOff": "0,1,2,3,4,5,6,7"
1169 "EventCode": "0xC5",
1170 "Counter": "0,1,2,3",
1171 "UMask": "0x2",
1174 …ption": "Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS).",
1175 "CounterHTOff": "0,1,2,3,4,5,6,7"
1179 … "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
1180 "EventCode": "0xC5",
1181 "Counter": "0,1,2,3",
1182 "UMask": "0x4",
1185 … "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
1186 "CounterHTOff": "0,1,2,3"
1190 "EventCode": "0xC5",
1191 "Counter": "0,1,2,3",
1192 "UMask": "0x10",
1195 … "BriefDescription": "Mispredicted not taken branch instructions retired.(Precise Event - PEBS).",
1196 "CounterHTOff": "0,1,2,3,4,5,6,7"
1200 "EventCode": "0xC5",
1201 "Counter": "0,1,2,3",
1202 "UMask": "0x20",
1205 … "BriefDescription": "Mispredicted taken branch instructions retired. (Precise Event - PEBS).",
1206 "CounterHTOff": "0,1,2,3,4,5,6,7"
1209 "EventCode": "0xCC",
1210 "Counter": "0,1,2,3",
1211 "UMask": "0x20",
1215 "CounterHTOff": "0,1,2,3,4,5,6,7"
1218 "EventCode": "0xE6",
1219 "Counter": "0,1,2,3",
1220 "UMask": "0x1f",
1224 "CounterHTOff": "0,1,2,3,4,5,6,7"