Lines Matching +full:1 +full:- +full:5
3 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
4 "Counter": "Fixed counter 1",
9 "CounterHTOff": "Fixed counter 1"
31 "Counter": "0,1,2,3",
35 "BriefDescription": "Not taken macro-conditional branches.",
36 "CounterHTOff": "0,1,2,3,4,5,6,7"
40 "Counter": "0,1,2,3",
44 "BriefDescription": "Taken speculative and retired macro-conditional branches.",
45 "CounterHTOff": "0,1,2,3,4,5,6,7"
49 "Counter": "0,1,2,3",
53 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
54 "CounterHTOff": "0,1,2,3,4,5,6,7"
58 "Counter": "0,1,2,3",
63 "CounterHTOff": "0,1,2,3,4,5,6,7"
67 "Counter": "0,1,2,3",
72 "CounterHTOff": "0,1,2,3,4,5,6,7"
76 "Counter": "0,1,2,3",
81 "CounterHTOff": "0,1,2,3,4,5,6,7"
85 "Counter": "0,1,2,3",
90 "CounterHTOff": "0,1,2,3,4,5,6,7"
94 "Counter": "0,1,2,3",
98 "BriefDescription": "Speculative and retired macro-conditional branches.",
99 "CounterHTOff": "0,1,2,3,4,5,6,7"
103 "Counter": "0,1,2,3",
107 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
108 "CounterHTOff": "0,1,2,3,4,5,6,7"
112 "Counter": "0,1,2,3",
117 "CounterHTOff": "0,1,2,3,4,5,6,7"
121 "Counter": "0,1,2,3",
126 "CounterHTOff": "0,1,2,3,4,5,6,7"
130 "Counter": "0,1,2,3",
135 "CounterHTOff": "0,1,2,3,4,5,6,7"
139 "Counter": "0,1,2,3",
144 "CounterHTOff": "0,1,2,3,4,5,6,7"
148 "Counter": "0,1,2,3",
153 "CounterHTOff": "0,1,2,3,4,5,6,7"
157 "Counter": "0,1,2,3",
162 "CounterHTOff": "0,1,2,3,4,5,6,7"
166 "Counter": "0,1,2,3",
171 "CounterHTOff": "0,1,2,3,4,5,6,7"
175 "Counter": "0,1,2,3",
180 "CounterHTOff": "0,1,2,3,4,5,6,7"
184 "Counter": "0,1,2,3",
189 "CounterHTOff": "0,1,2,3,4,5,6,7"
193 "Counter": "0,1,2,3",
198 "CounterHTOff": "0,1,2,3,4,5,6,7"
202 "Counter": "0,1,2,3",
207 "CounterHTOff": "0,1,2,3,4,5,6,7"
211 "Counter": "0,1,2,3",
216 "CounterHTOff": "0,1,2,3,4,5,6,7"
220 "Counter": "0,1,2,3",
225 "CounterHTOff": "0,1,2,3,4,5,6,7"
229 "Counter": "0,1,2,3",
234 "CounterHTOff": "0,1,2,3,4,5,6,7"
238 "Counter": "0,1,2,3",
243 "CounterMask": "1",
244 "CounterHTOff": "0,1,2,3,4,5,6,7"
248 "Counter": "0,1,2,3",
253 "CounterHTOff": "0,1,2,3,4,5,6,7"
257 "Counter": "0,1,2,3",
262 "CounterHTOff": "0,1,2,3,4,5,6,7"
266 "Counter": "0,1,2,3",
271 "CounterHTOff": "0,1,2,3,4,5,6,7"
275 "Counter": "0,1,2,3",
279 "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
280 "CounterHTOff": "0,1,2,3,4,5,6,7"
283 … where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and I…
285 "Counter": "0,1,2,3",
290 "CounterHTOff": "0,1,2,3,4,5,6,7"
294 "Counter": "0,1,2,3",
299 "CounterHTOff": "0,1,2,3,4,5,6,7"
303 "Counter": "0,1,2,3",
307 "BriefDescription": "Resource-related stall cycles.",
308 "CounterHTOff": "0,1,2,3,4,5,6,7"
312 "Counter": "0,1,2,3",
317 "CounterHTOff": "0,1,2,3,4,5,6,7"
321 "Counter": "0,1,2,3",
326 "CounterHTOff": "0,1,2,3,4,5,6,7"
330 "Counter": "0,1,2,3",
335 "CounterHTOff": "0,1,2,3,4,5,6,7"
339 "Counter": "0,1,2,3",
343 "BriefDescription": "Cycles stalled due to re-order buffer full.",
344 "CounterHTOff": "0,1,2,3,4,5,6,7"
348 "Counter": "0,1,2,3",
353 "CounterHTOff": "0,1,2,3,4,5,6,7"
356 …": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
358 "Counter": "0,1,2,3",
363 "CounterHTOff": "0,1,2,3,4,5,6,7"
367 "Invert": "1",
368 "Counter": "0,1,2,3",
373 "CounterMask": "1",
374 "CounterHTOff": "0,1,2,3"
378 "Invert": "1",
379 "Counter": "0,1,2,3",
381 "AnyThread": "1",
385 "CounterMask": "1",
386 "CounterHTOff": "0,1,2,3"
390 "Counter": "0,1,2,3",
395 "CounterHTOff": "0,1,2,3,4,5,6,7"
399 "Counter": "0,1,2,3",
404 "CounterHTOff": "0,1,2,3,4,5,6,7"
407 …"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which …
409 "Counter": "0,1,2,3",
413 "BriefDescription": "Self-modifying code (SMC) detected.",
414 "CounterHTOff": "0,1,2,3,4,5,6,7"
417 …"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flo…
419 "Counter": "0,1,2,3",
424 "CounterHTOff": "0,1,2,3,4,5,6,7"
428 "Counter": "0,1,2,3",
432 … "BriefDescription": "Number of instructions retired. General Counter - architectural event.",
433 "CounterHTOff": "0,1,2,3,4,5,6,7"
436 "PEBS": "1",
437 "PublicDescription": "This event counts the number of micro-ops retired.",
439 "Counter": "0,1,2,3",
444 "CounterHTOff": "0,1,2,3,4,5,6,7"
447 "PEBS": "1",
448 …h cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in d…
450 "Counter": "0,1,2,3",
455 "CounterHTOff": "0,1,2,3,4,5,6,7"
459 "Invert": "1",
460 "Counter": "0,1,2,3",
465 "CounterMask": "1",
466 "CounterHTOff": "0,1,2,3"
470 "Invert": "1",
471 "Counter": "0,1,2,3",
477 "CounterHTOff": "0,1,2,3"
480 "PEBS": "1",
482 "Counter": "0,1,2,3",
487 "CounterHTOff": "0,1,2,3,4,5,6,7"
490 "PEBS": "1",
492 "Counter": "0,1,2,3",
497 "CounterHTOff": "0,1,2,3,4,5,6,7"
501 "Counter": "0,1,2,3",
506 "CounterHTOff": "0,1,2,3,4,5,6,7"
509 "PEBS": "1",
511 "Counter": "0,1,2,3",
516 "CounterHTOff": "0,1,2,3,4,5,6,7"
520 "Counter": "0,1,2,3",
525 "CounterHTOff": "0,1,2,3,4,5,6,7"
528 "PEBS": "1",
530 "Counter": "0,1,2,3",
535 "CounterHTOff": "0,1,2,3,4,5,6,7"
539 "Counter": "0,1,2,3",
544 "CounterHTOff": "0,1,2,3,4,5,6,7"
549 "Counter": "0,1,2,3",
553 "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
554 "CounterHTOff": "0,1,2,3"
557 "PEBS": "1",
559 "Counter": "0,1,2,3",
564 "CounterHTOff": "0,1,2,3,4,5,6,7"
567 "PEBS": "1",
569 "Counter": "0,1,2,3",
574 "CounterHTOff": "0,1,2,3,4,5,6,7"
578 "Counter": "0,1,2,3",
583 "CounterHTOff": "0,1,2,3,4,5,6,7"
586 "PEBS": "1",
588 "Counter": "0,1,2,3",
593 "CounterHTOff": "0,1,2,3,4,5,6,7"
596 "PEBS": "1",
598 "Counter": "0,1,2,3",
603 "CounterHTOff": "0,1,2,3,4,5,6,7"
607 … "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
609 "Counter": "0,1,2,3",
613 … "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
614 "CounterHTOff": "0,1,2,3"
618 "Counter": "0,1,2,3",
623 "CounterHTOff": "0,1,2,3,4,5,6,7"
627 "Counter": "0,1,2,3",
632 "CounterHTOff": "0,1,2,3,4,5,6,7"
637 "Counter": "0,1,2,3",
639 "EdgeDetect": "1",
643 "CounterMask": "1",
644 "CounterHTOff": "0,1,2,3,4,5,6,7"
648 "Counter": "0,1,2,3",
653 "CounterHTOff": "0,1,2,3,4,5,6,7"
657 "Counter": "0,1,2,3",
662 "CounterHTOff": "0,1,2,3,4,5,6,7"
666 "Counter": "0,1,2,3",
671 "CounterHTOff": "0,1,2,3,4,5,6,7"
675 "Counter": "0,1,2,3",
679 "BriefDescription": "Cycles per thread when uops are dispatched to port 1.",
680 "CounterHTOff": "0,1,2,3,4,5,6,7"
684 "Counter": "0,1,2,3",
689 "CounterHTOff": "0,1,2,3,4,5,6,7"
693 "Counter": "0,1,2,3",
697 "BriefDescription": "Cycles per thread when uops are dispatched to port 5.",
698 "CounterHTOff": "0,1,2,3,4,5,6,7"
702 "Counter": "0,1,2,3",
706 …"BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this i…
708 "CounterHTOff": "0,1,2,3"
716 …miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1…
722 "Counter": "0,1,2,3",
726 …s a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for dema…
727 "CounterMask": "1",
728 "CounterHTOff": "0,1,2,3,4,5,6,7"
736 …-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and c…
742 "Counter": "0,1,2,3",
746 …-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry…
747 "CounterMask": "5",
748 "CounterHTOff": "0,1,2,3"
752 "Counter": "0,1,2,3",
756 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
757 "CounterHTOff": "0,1,2,3,4,5,6,7"
761 "Counter": "0,1,2,3",
765 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
766 "CounterHTOff": "0,1,2,3,4,5,6,7"
770 "Counter": "0,1,2,3",
775 "CounterHTOff": "0,1,2,3,4,5,6,7"
778 …tore. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Opti…
780 "Counter": "0,1,2,3",
784 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
785 "CounterHTOff": "0,1,2,3,4,5,6,7"
789 "Counter": "0,1,2,3",
794 "CounterHTOff": "0,1,2,3,4,5,6,7"
798 "Counter": "0,1,2,3",
802 …"BriefDescription": "Number of cases where any load ends up with a valid block-code written to the…
803 "CounterHTOff": "0,1,2,3,4,5,6,7"
806 …eck in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.",
808 "Counter": "0,1,2,3",
813 "CounterHTOff": "0,1,2,3,4,5,6,7"
817 "Counter": "0,1,2,3",
822 "CounterHTOff": "0,1,2,3,4,5,6,7"
826 "Counter": "0,1,2,3",
830 …perations with all the following traits: 1. addressing of the format [base + offset], 2. the offse…
831 "CounterHTOff": "0,1,2,3,4,5,6,7"
835 "Counter": "0,1,2,3",
840 "CounterHTOff": "0,1,2,3,4,5,6,7"
844 "Counter": "0,1,2,3",
849 "CounterHTOff": "0,1,2,3"
853 "Counter": "0,1,2,3",
855 "AnyThread": "1",
859 "CounterHTOff": "0,1,2,3,4,5,6,7"
863 "Counter": "0,1,2,3",
865 "AnyThread": "1",
868 "BriefDescription": "Cycles per core when uops are dispatched to port 1.",
869 "CounterHTOff": "0,1,2,3,4,5,6,7"
873 "Counter": "0,1,2,3",
875 "AnyThread": "1",
879 "CounterHTOff": "0,1,2,3,4,5,6,7"
883 "Counter": "0,1,2,3",
885 "AnyThread": "1",
888 "BriefDescription": "Cycles per core when uops are dispatched to port 5.",
889 "CounterHTOff": "0,1,2,3,4,5,6,7"
893 "Counter": "0,1,2,3",
898 "CounterHTOff": "0,1,2,3,4,5,6,7"
902 "Counter": "0,1,2,3",
907 "CounterHTOff": "0,1,2,3,4,5,6,7"
911 "Counter": "0,1,2,3",
913 "AnyThread": "1",
917 "CounterHTOff": "0,1,2,3,4,5,6,7"
921 "Counter": "0,1,2,3",
923 "AnyThread": "1",
927 "CounterHTOff": "0,1,2,3,4,5,6,7"
932 "Counter": "1",
936 "BriefDescription": "Instructions retired. (Precise Event - PEBS).",
937 "TakenAlone": "1",
938 "CounterHTOff": "1"
942 "Counter": "0,1,2,3",
947 "CounterHTOff": "0,1,2,3,4,5,6,7"
951 "Counter": "0,1,2,3",
956 "CounterHTOff": "0,1,2,3,4,5,6,7"
960 "Counter": "0,1,2,3",
965 "CounterHTOff": "0,1,2,3,4,5,6,7"
969 "Counter": "0,1,2,3",
974 "CounterHTOff": "0,1,2,3,4,5,6,7"
978 "Counter": "0,1,2,3",
983 "CounterHTOff": "0,1,2,3,4,5,6,7"
987 "Counter": "0,1,2,3",
992 "CounterHTOff": "0,1,2,3,4,5,6,7"
996 "Counter": "0,1,2,3",
1001 "CounterMask": "1",
1002 "CounterHTOff": "0,1,2,3,4,5,6,7"
1005 …cuting performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For mo…
1007 "Counter": "0,1,2,3",
1011 … "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
1012 "CounterMask": "1",
1013 "CounterHTOff": "0,1,2,3,4,5,6,7"
1017 "Counter": "0,1,2,3",
1019 "EdgeDetect": "1",
1023 "CounterMask": "1",
1024 "CounterHTOff": "0,1,2,3,4,5,6,7"
1028 "Counter": "0,1,2,3",
1033 "CounterHTOff": "0,1,2,3,4,5,6,7"
1037 "Counter": "0,1,2,3",
1042 "CounterHTOff": "0,1,2,3,4,5,6,7"
1046 "Counter": "0,1,2,3",
1051 "CounterHTOff": "0,1,2,3,4,5,6,7"
1055 "Invert": "1",
1056 "Counter": "0,1,2,3",
1061 "CounterMask": "1",
1062 "CounterHTOff": "0,1,2,3"
1066 "Counter": "0,1,2,3",
1072 "CounterHTOff": "0,1,2,3,4,5,6,7"
1076 "Counter": "0,1,2,3",
1078 "EdgeDetect": "1",
1082 "CounterMask": "1",
1083 "CounterHTOff": "0,1,2,3,4,5,6,7"
1087 "Invert": "1",
1088 "Counter": "0,1,2,3",
1090 "EdgeDetect": "1",
1094 "CounterMask": "1",
1095 "CounterHTOff": "0,1,2,3,4,5,6,7"
1100 "AnyThread": "1",
1108 "Counter": "0,1,2,3",
1110 "AnyThread": "1",
1114 "CounterHTOff": "0,1,2,3,4,5,6,7"
1118 "Counter": "0,1,2,3",
1120 "AnyThread": "1",
1124 "CounterHTOff": "0,1,2,3,4,5,6,7"
1128 "Counter": "0,1,2,3",
1130 "AnyThread": "1",
1134 "CounterMask": "1",
1135 "CounterHTOff": "0,1,2,3,4,5,6,7"
1139 "Counter": "0,1,2,3",
1143 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1144 "CounterMask": "1",
1145 "CounterHTOff": "0,1,2,3,4,5,6,7"
1149 "Counter": "0,1,2,3",
1153 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1155 "CounterHTOff": "0,1,2,3,4,5,6,7"
1159 "Counter": "0,1,2,3",
1163 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1165 "CounterHTOff": "0,1,2,3,4,5,6,7"
1169 "Counter": "0,1,2,3",
1173 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1175 "CounterHTOff": "0,1,2,3,4,5,6,7"
1179 "Invert": "1",
1180 "Counter": "0,1,2,3",
1184 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1185 "CounterHTOff": "0,1,2,3,4,5,6,7"
1190 "Counter": "0,1,2,3",
1195 "CounterHTOff": "0,1,2,3,4,5,6,7"
1199 "Counter": "0,1,2,3",
1201 "AnyThread": "1",
1205 "CounterHTOff": "0,1,2,3,4,5,6,7"
1209 "Counter": "0,1,2,3",
1214 "CounterHTOff": "0,1,2,3,4,5,6,7"