Lines Matching +full:0 +full:- +full:3
4 "EventCode": "0xD0",
5 "Counter": "0,1,2,3",
6 "UMask": "0x11",
10 "CounterHTOff": "0,1,2,3"
14 "EventCode": "0xD0",
15 "Counter": "0,1,2,3",
16 "UMask": "0x12",
20 "CounterHTOff": "0,1,2,3"
24 "EventCode": "0xD0",
25 "Counter": "0,1,2,3",
26 "UMask": "0x21",
30 "CounterHTOff": "0,1,2,3"
34 …ription": "This event counts line-splitted load uops retired to the architected path. A line split…
35 "EventCode": "0xD0",
36 "Counter": "0,1,2,3",
37 "UMask": "0x41",
41 "CounterHTOff": "0,1,2,3"
45 …ription": "This event counts line-splitted store uops retired to the architected path. A line spli…
46 "EventCode": "0xD0",
47 "Counter": "0,1,2,3",
48 "UMask": "0x42",
52 "CounterHTOff": "0,1,2,3"
57 "EventCode": "0xD0",
58 "Counter": "0,1,2,3",
59 "UMask": "0x81",
63 "CounterHTOff": "0,1,2,3"
68 "EventCode": "0xD0",
69 "Counter": "0,1,2,3",
70 "UMask": "0x82",
74 "CounterHTOff": "0,1,2,3"
78 "EventCode": "0xD1",
79 "Counter": "0,1,2,3",
80 "UMask": "0x1",
84 "CounterHTOff": "0,1,2,3"
88 "EventCode": "0xD1",
89 "Counter": "0,1,2,3",
90 "UMask": "0x2",
94 "CounterHTOff": "0,1,2,3"
97 …"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache wi…
98 "EventCode": "0xD1",
99 "Counter": "0,1,2,3",
100 "UMask": "0x4",
104 "CounterHTOff": "0,1,2,3"
107 "EventCode": "0xD1",
108 "Counter": "0,1,2,3",
109 "UMask": "0x20",
112 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
113 "CounterHTOff": "0,1,2,3"
117 "EventCode": "0xD1",
118 "Counter": "0,1,2,3",
119 "UMask": "0x40",
123 "CounterHTOff": "0,1,2,3"
126 "EventCode": "0xD2",
127 "Counter": "0,1,2,3",
128 "UMask": "0x1",
131 …n": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core …
132 "CounterHTOff": "0,1,2,3"
135 …-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (sa…
136 "EventCode": "0xD2",
137 "Counter": "0,1,2,3",
138 "UMask": "0x2",
141 …iption": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core c…
142 "CounterHTOff": "0,1,2,3"
145 …his event counts retired load uops that hit in the last-level cache (L3) and were found in a non-m…
146 "EventCode": "0xD2",
147 "Counter": "0,1,2,3",
148 "UMask": "0x4",
152 "CounterHTOff": "0,1,2,3"
155 "EventCode": "0xD2",
156 "Counter": "0,1,2,3",
157 "UMask": "0x8",
161 "CounterHTOff": "0,1,2,3"
164 "EventCode": "0xD3",
165 "Counter": "0,1,2,3",
166 "UMask": "0x1",
170 "CounterHTOff": "0,1,2,3"
173 "EventCode": "0xD3",
174 "Counter": "0,1,2,3",
175 "UMask": "0x4",
179 "CounterHTOff": "0,1,2,3"
183 "EventCode": "0x51",
184 "Counter": "0,1,2,3",
185 "UMask": "0x1",
189 "CounterHTOff": "0,1,2,3,4,5,6,7"
192 "EventCode": "0x51",
193 "Counter": "0,1,2,3",
194 "UMask": "0x2",
198 "CounterHTOff": "0,1,2,3,4,5,6,7"
201 "EventCode": "0x51",
202 "Counter": "0,1,2,3",
203 "UMask": "0x4",
207 "CounterHTOff": "0,1,2,3,4,5,6,7"
210 "EventCode": "0x51",
211 "Counter": "0,1,2,3",
212 "UMask": "0x8",
216 "CounterHTOff": "0,1,2,3,4,5,6,7"
219 "EventCode": "0x48",
221 "UMask": "0x1",
228 "EventCode": "0x48",
230 "UMask": "0x1",
238 "EventCode": "0x63",
239 "Counter": "0,1,2,3",
240 "UMask": "0x2",
244 "CounterHTOff": "0,1,2,3,4,5,6,7"
247 "EventCode": "0x60",
248 "Counter": "0,1,2,3",
249 "UMask": "0x1",
253 "CounterHTOff": "0,1,2,3,4,5,6,7"
256 "EventCode": "0x60",
257 "Counter": "0,1,2,3",
258 "UMask": "0x1",
263 "CounterHTOff": "0,1,2,3,4,5,6,7"
266 "EventCode": "0x60",
267 "Counter": "0,1,2,3",
268 "UMask": "0x4",
272 "CounterHTOff": "0,1,2,3,4,5,6,7"
275 "EventCode": "0x60",
276 "Counter": "0,1,2,3",
277 "UMask": "0x8",
281 "CounterHTOff": "0,1,2,3,4,5,6,7"
284 "EventCode": "0x60",
285 "Counter": "0,1,2,3",
286 "UMask": "0x8",
291 "CounterHTOff": "0,1,2,3,4,5,6,7"
294 "EventCode": "0xB0",
295 "Counter": "0,1,2,3",
296 "UMask": "0x1",
300 "CounterHTOff": "0,1,2,3,4,5,6,7"
303 "EventCode": "0xB0",
304 "Counter": "0,1,2,3",
305 "UMask": "0x2",
309 "CounterHTOff": "0,1,2,3,4,5,6,7"
312 "EventCode": "0xB0",
313 "Counter": "0,1,2,3",
314 "UMask": "0x4",
318 "CounterHTOff": "0,1,2,3,4,5,6,7"
321 "EventCode": "0xB0",
322 "Counter": "0,1,2,3",
323 "UMask": "0x8",
327 "CounterHTOff": "0,1,2,3,4,5,6,7"
330 "EventCode": "0xB2",
331 "Counter": "0,1,2,3",
332 "UMask": "0x1",
336 "CounterHTOff": "0,1,2,3,4,5,6,7"
339 "EventCode": "0x24",
340 "Counter": "0,1,2,3",
341 "UMask": "0x1",
345 "CounterHTOff": "0,1,2,3,4,5,6,7"
348 "EventCode": "0x24",
349 "Counter": "0,1,2,3",
350 "UMask": "0x4",
354 "CounterHTOff": "0,1,2,3,4,5,6,7"
357 "EventCode": "0x24",
358 "Counter": "0,1,2,3",
359 "UMask": "0x8",
363 "CounterHTOff": "0,1,2,3,4,5,6,7"
366 "EventCode": "0x24",
367 "Counter": "0,1,2,3",
368 "UMask": "0x10",
372 "CounterHTOff": "0,1,2,3,4,5,6,7"
375 "EventCode": "0x24",
376 "Counter": "0,1,2,3",
377 "UMask": "0x20",
381 "CounterHTOff": "0,1,2,3,4,5,6,7"
384 "EventCode": "0x24",
385 "Counter": "0,1,2,3",
386 "UMask": "0x40",
390 "CounterHTOff": "0,1,2,3,4,5,6,7"
393 "EventCode": "0x24",
394 "Counter": "0,1,2,3",
395 "UMask": "0x80",
399 "CounterHTOff": "0,1,2,3,4,5,6,7"
402 "EventCode": "0x27",
403 "Counter": "0,1,2,3",
404 "UMask": "0x1",
408 "CounterHTOff": "0,1,2,3,4,5,6,7"
411 "EventCode": "0x27",
412 "Counter": "0,1,2,3",
413 "UMask": "0x4",
417 "CounterHTOff": "0,1,2,3,4,5,6,7"
420 "EventCode": "0x27",
421 "Counter": "0,1,2,3",
422 "UMask": "0x8",
426 "CounterHTOff": "0,1,2,3,4,5,6,7"
429 "EventCode": "0x27",
430 "Counter": "0,1,2,3",
431 "UMask": "0xf",
435 "CounterHTOff": "0,1,2,3,4,5,6,7"
438 "EventCode": "0x28",
439 "Counter": "0,1,2,3",
440 "UMask": "0x1",
443 …on": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the…
444 "CounterHTOff": "0,1,2,3,4,5,6,7"
447 "EventCode": "0x28",
448 "Counter": "0,1,2,3",
449 "UMask": "0x2",
453 "CounterHTOff": "0,1,2,3,4,5,6,7"
456 "EventCode": "0x28",
457 "Counter": "0,1,2,3",
458 "UMask": "0x4",
462 "CounterHTOff": "0,1,2,3,4,5,6,7"
465 "EventCode": "0x28",
466 "Counter": "0,1,2,3",
467 "UMask": "0x8",
471 "CounterHTOff": "0,1,2,3,4,5,6,7"
474 "EventCode": "0x28",
475 "Counter": "0,1,2,3",
476 "UMask": "0xf",
480 "CounterHTOff": "0,1,2,3,4,5,6,7"
483 "EventCode": "0xF0",
484 "Counter": "0,1,2,3",
485 "UMask": "0x1",
489 "CounterHTOff": "0,1,2,3,4,5,6,7"
492 "EventCode": "0xF0",
493 "Counter": "0,1,2,3",
494 "UMask": "0x2",
498 "CounterHTOff": "0,1,2,3,4,5,6,7"
501 "EventCode": "0xF0",
502 "Counter": "0,1,2,3",
503 "UMask": "0x4",
507 "CounterHTOff": "0,1,2,3,4,5,6,7"
510 "EventCode": "0xF0",
511 "Counter": "0,1,2,3",
512 "UMask": "0x8",
516 "CounterHTOff": "0,1,2,3,4,5,6,7"
519 "EventCode": "0xF0",
520 "Counter": "0,1,2,3",
521 "UMask": "0x10",
525 "CounterHTOff": "0,1,2,3,4,5,6,7"
528 "EventCode": "0xF0",
529 "Counter": "0,1,2,3",
530 "UMask": "0x20",
534 "CounterHTOff": "0,1,2,3,4,5,6,7"
537 "EventCode": "0xF0",
538 "Counter": "0,1,2,3",
539 "UMask": "0x40",
543 "CounterHTOff": "0,1,2,3,4,5,6,7"
546 "EventCode": "0xF0",
547 "Counter": "0,1,2,3",
548 "UMask": "0x80",
552 "CounterHTOff": "0,1,2,3,4,5,6,7"
555 "EventCode": "0xF1",
556 "Counter": "0,1,2,3",
557 "UMask": "0x1",
561 "CounterHTOff": "0,1,2,3,4,5,6,7"
564 "EventCode": "0xF1",
565 "Counter": "0,1,2,3",
566 "UMask": "0x2",
570 "CounterHTOff": "0,1,2,3,4,5,6,7"
573 "EventCode": "0xF1",
574 "Counter": "0,1,2,3",
575 "UMask": "0x4",
579 "CounterHTOff": "0,1,2,3,4,5,6,7"
583 "EventCode": "0xF1",
584 "Counter": "0,1,2,3",
585 "UMask": "0x7",
589 "CounterHTOff": "0,1,2,3,4,5,6,7"
592 "EventCode": "0xF2",
593 "Counter": "0,1,2,3",
594 "UMask": "0x1",
598 "CounterHTOff": "0,1,2,3,4,5,6,7"
601 "EventCode": "0xF2",
602 "Counter": "0,1,2,3",
603 "UMask": "0x2",
607 "CounterHTOff": "0,1,2,3,4,5,6,7"
610 "EventCode": "0xF2",
611 "Counter": "0,1,2,3",
612 "UMask": "0x4",
616 "CounterHTOff": "0,1,2,3,4,5,6,7"
619 "EventCode": "0xF2",
620 "Counter": "0,1,2,3",
621 "UMask": "0x8",
625 "CounterHTOff": "0,1,2,3,4,5,6,7"
628 "EventCode": "0xF2",
629 "Counter": "0,1,2,3",
630 "UMask": "0xa",
634 "CounterHTOff": "0,1,2,3,4,5,6,7"
637 "EventCode": "0x2E",
638 "Counter": "0,1,2,3",
639 "UMask": "0x41",
642 "BriefDescription": "Core-originated cacheable demand requests missed LLC.",
643 "CounterHTOff": "0,1,2,3,4,5,6,7"
646 "EventCode": "0x2E",
647 "Counter": "0,1,2,3",
648 "UMask": "0x4f",
651 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.",
652 "CounterHTOff": "0,1,2,3,4,5,6,7"
655 "EventCode": "0xF4",
656 "Counter": "0,1,2,3",
657 "UMask": "0x10",
661 "CounterHTOff": "0,1,2,3,4,5,6,7"
664 "EventCode": "0x24",
665 "Counter": "0,1,2,3",
666 "UMask": "0x3",
670 "CounterHTOff": "0,1,2,3,4,5,6,7"
673 "EventCode": "0x24",
674 "Counter": "0,1,2,3",
675 "UMask": "0xc",
679 "CounterHTOff": "0,1,2,3,4,5,6,7"
682 "EventCode": "0x24",
683 "Counter": "0,1,2,3",
684 "UMask": "0x30",
688 "CounterHTOff": "0,1,2,3,4,5,6,7"
691 "EventCode": "0x24",
692 "Counter": "0,1,2,3",
693 "UMask": "0xc0",
697 "CounterHTOff": "0,1,2,3,4,5,6,7"
700 "EventCode": "0xBF",
701 "Counter": "0,1,2,3",
702 "UMask": "0x5",
707 "CounterHTOff": "0,1,2,3,4,5,6,7"
710 "EventCode": "0x60",
711 "Counter": "0,1,2,3",
712 "UMask": "0x4",
717 "CounterHTOff": "0,1,2,3,4,5,6,7"
720 "EventCode": "0x60",
721 "Counter": "0,1,2,3",
722 "UMask": "0x1",
727 "CounterHTOff": "0,1,2,3,4,5,6,7"
730 "EventCode": "0x48",
732 "UMask": "0x1",
741 "EventCode": "0x48",
742 "Counter": "0,1,2,3",
743 "UMask": "0x2",
748 "CounterHTOff": "0,1,2,3,4,5,6,7"
751 "EventCode": "0xB7, 0xBB",
752 "MSRValue": "0x4003c0091",
753 "Counter": "0,1,2,3",
754 "UMask": "0x1",
757 "MSRIndex": "0x1a6,0x1a7",
760 "CounterHTOff": "0,1,2,3"
763 "EventCode": "0xB7, 0xBB",
764 "MSRValue": "0x10003c0091",
765 "Counter": "0,1,2,3",
766 "UMask": "0x1",
769 "MSRIndex": "0x1a6,0x1a7",
772 "CounterHTOff": "0,1,2,3"
775 "EventCode": "0xB7, 0xBB",
776 "MSRValue": "0x1003c0091",
777 "Counter": "0,1,2,3",
778 "UMask": "0x1",
781 "MSRIndex": "0x1a6,0x1a7",
783 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
784 "CounterHTOff": "0,1,2,3"
787 "EventCode": "0xB7, 0xBB",
788 "MSRValue": "0x2003c0091",
789 "Counter": "0,1,2,3",
790 "UMask": "0x1",
793 "MSRIndex": "0x1a6,0x1a7",
796 "CounterHTOff": "0,1,2,3"
799 "EventCode": "0xB7, 0xBB",
800 "MSRValue": "0x3f803c0090",
801 "Counter": "0,1,2,3",
802 "UMask": "0x1",
805 "MSRIndex": "0x1a6,0x1a7",
808 "CounterHTOff": "0,1,2,3"
811 "EventCode": "0xB7, 0xBB",
812 "MSRValue": "0x4003c0090",
813 "Counter": "0,1,2,3",
814 "UMask": "0x1",
817 "MSRIndex": "0x1a6,0x1a7",
820 "CounterHTOff": "0,1,2,3"
823 "EventCode": "0xB7, 0xBB",
824 "MSRValue": "0x10003c0090",
825 "Counter": "0,1,2,3",
826 "UMask": "0x1",
829 "MSRIndex": "0x1a6,0x1a7",
832 "CounterHTOff": "0,1,2,3"
835 "EventCode": "0xB7, 0xBB",
836 "MSRValue": "0x1003c0090",
837 "Counter": "0,1,2,3",
838 "UMask": "0x1",
841 "MSRIndex": "0x1a6,0x1a7",
843 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
844 "CounterHTOff": "0,1,2,3"
847 "EventCode": "0xB7, 0xBB",
848 "MSRValue": "0x2003c0090",
849 "Counter": "0,1,2,3",
850 "UMask": "0x1",
853 "MSRIndex": "0x1a6,0x1a7",
856 "CounterHTOff": "0,1,2,3"
859 "EventCode": "0xB7, 0xBB",
860 "MSRValue": "0x3f803c03f7",
861 "Counter": "0,1,2,3",
862 "UMask": "0x1",
865 "MSRIndex": "0x1a6,0x1a7",
868 "CounterHTOff": "0,1,2,3"
871 "EventCode": "0xB7, 0xBB",
872 "MSRValue": "0x4003c03f7",
873 "Counter": "0,1,2,3",
874 "UMask": "0x1",
877 "MSRIndex": "0x1a6,0x1a7",
880 "CounterHTOff": "0,1,2,3"
883 "EventCode": "0xB7, 0xBB",
884 "MSRValue": "0x10003c03f7",
885 "Counter": "0,1,2,3",
886 "UMask": "0x1",
889 "MSRIndex": "0x1a6,0x1a7",
892 "CounterHTOff": "0,1,2,3"
895 "EventCode": "0xB7, 0xBB",
896 "MSRValue": "0x1003c03f7",
897 "Counter": "0,1,2,3",
898 "UMask": "0x1",
901 "MSRIndex": "0x1a6,0x1a7",
903 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
904 "CounterHTOff": "0,1,2,3"
907 "EventCode": "0xB7, 0xBB",
908 "MSRValue": "0x2003c03f7",
909 "Counter": "0,1,2,3",
910 "UMask": "0x1",
913 "MSRIndex": "0x1a6,0x1a7",
916 "CounterHTOff": "0,1,2,3"
919 "EventCode": "0xB7, 0xBB",
920 "MSRValue": "0x10008",
921 "Counter": "0,1,2,3",
922 "UMask": "0x1",
925 "MSRIndex": "0x1a6,0x1a7",
928 "CounterHTOff": "0,1,2,3"
931 "EventCode": "0xB7, 0xBB",
932 "MSRValue": "0x3f803c0004",
933 "Counter": "0,1,2,3",
934 "UMask": "0x1",
937 "MSRIndex": "0x1a6,0x1a7",
940 "CounterHTOff": "0,1,2,3"
943 "EventCode": "0xB7, 0xBB",
944 "MSRValue": "0x3f803c0001",
945 "Counter": "0,1,2,3",
946 "UMask": "0x1",
949 "MSRIndex": "0x1a6,0x1a7",
952 "CounterHTOff": "0,1,2,3"
955 "EventCode": "0xB7, 0xBB",
956 "MSRValue": "0x4003c0001",
957 "Counter": "0,1,2,3",
958 "UMask": "0x1",
961 "MSRIndex": "0x1a6,0x1a7",
964 "CounterHTOff": "0,1,2,3"
967 "EventCode": "0xB7, 0xBB",
968 "MSRValue": "0x10003c0001",
969 "Counter": "0,1,2,3",
970 "UMask": "0x1",
973 "MSRIndex": "0x1a6,0x1a7",
976 "CounterHTOff": "0,1,2,3"
979 "EventCode": "0xB7, 0xBB",
980 "MSRValue": "0x1003c0001",
981 "Counter": "0,1,2,3",
982 "UMask": "0x1",
985 "MSRIndex": "0x1a6,0x1a7",
987 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
988 "CounterHTOff": "0,1,2,3"
991 "EventCode": "0xB7, 0xBB",
992 "MSRValue": "0x2003c0001",
993 "Counter": "0,1,2,3",
994 "UMask": "0x1",
997 "MSRIndex": "0x1a6,0x1a7",
1000 "CounterHTOff": "0,1,2,3"
1003 "EventCode": "0xB7, 0xBB",
1004 "MSRValue": "0x803c8000",
1005 "Counter": "0,1,2,3",
1006 "UMask": "0x1",
1009 "MSRIndex": "0x1a6,0x1a7",
1012 "CounterHTOff": "0,1,2,3"
1015 "EventCode": "0xB7, 0xBB",
1016 "MSRValue": "0x23ffc08000",
1017 "Counter": "0,1,2,3",
1018 "UMask": "0x1",
1021 "MSRIndex": "0x1a6,0x1a7",
1024 "CounterHTOff": "0,1,2,3"
1027 "EventCode": "0xB7, 0xBB",
1028 "MSRValue": "0x3f803c0040",
1029 "Counter": "0,1,2,3",
1030 "UMask": "0x1",
1033 "MSRIndex": "0x1a6,0x1a7",
1036 "CounterHTOff": "0,1,2,3"
1039 "EventCode": "0xB7, 0xBB",
1040 "MSRValue": "0x3f803c0010",
1041 "Counter": "0,1,2,3",
1042 "UMask": "0x1",
1045 "MSRIndex": "0x1a6,0x1a7",
1048 "CounterHTOff": "0,1,2,3"
1051 "EventCode": "0xB7, 0xBB",
1052 "MSRValue": "0x4003c0010",
1053 "Counter": "0,1,2,3",
1054 "UMask": "0x1",
1057 "MSRIndex": "0x1a6,0x1a7",
1060 "CounterHTOff": "0,1,2,3"
1063 "EventCode": "0xB7, 0xBB",
1064 "MSRValue": "0x10003c0010",
1065 "Counter": "0,1,2,3",
1066 "UMask": "0x1",
1069 "MSRIndex": "0x1a6,0x1a7",
1072 "CounterHTOff": "0,1,2,3"
1075 "EventCode": "0xB7, 0xBB",
1076 "MSRValue": "0x1003c0010",
1077 "Counter": "0,1,2,3",
1078 "UMask": "0x1",
1081 "MSRIndex": "0x1a6,0x1a7",
1083 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
1084 "CounterHTOff": "0,1,2,3"
1087 "EventCode": "0xB7, 0xBB",
1088 "MSRValue": "0x2003c0010",
1089 "Counter": "0,1,2,3",
1090 "UMask": "0x1",
1093 "MSRIndex": "0x1a6,0x1a7",
1096 "CounterHTOff": "0,1,2,3"
1099 "EventCode": "0xB7, 0xBB",
1100 "MSRValue": "0x3f803c0200",
1101 "Counter": "0,1,2,3",
1102 "UMask": "0x1",
1105 "MSRIndex": "0x1a6,0x1a7",
1108 "CounterHTOff": "0,1,2,3"
1111 "EventCode": "0xB7, 0xBB",
1112 "MSRValue": "0x3f803c0080",
1113 "Counter": "0,1,2,3",
1114 "UMask": "0x1",
1117 "MSRIndex": "0x1a6,0x1a7",
1120 "CounterHTOff": "0,1,2,3"
1123 "EventCode": "0xB7, 0xBB",
1124 "MSRValue": "0x4003c0080",
1125 "Counter": "0,1,2,3",
1126 "UMask": "0x1",
1129 "MSRIndex": "0x1a6,0x1a7",
1132 "CounterHTOff": "0,1,2,3"
1135 "EventCode": "0xB7, 0xBB",
1136 "MSRValue": "0x10003c0080",
1137 "Counter": "0,1,2,3",
1138 "UMask": "0x1",
1141 "MSRIndex": "0x1a6,0x1a7",
1144 "CounterHTOff": "0,1,2,3"
1147 "EventCode": "0xB7, 0xBB",
1148 "MSRValue": "0x1003c0080",
1149 "Counter": "0,1,2,3",
1150 "UMask": "0x1",
1153 "MSRIndex": "0x1a6,0x1a7",
1155 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
1156 "CounterHTOff": "0,1,2,3"
1159 "EventCode": "0xB7, 0xBB",
1160 "MSRValue": "0x2003c0080",
1161 "Counter": "0,1,2,3",
1162 "UMask": "0x1",
1165 "MSRIndex": "0x1a6,0x1a7",
1168 "CounterHTOff": "0,1,2,3"
1171 "EventCode": "0xB7, 0xBB",
1172 "MSRValue": "0x10400",
1173 "Counter": "0,1,2,3",
1174 "UMask": "0x1",
1177 "MSRIndex": "0x1a6,0x1a7",
1180 "CounterHTOff": "0,1,2,3"
1183 "EventCode": "0xB7, 0xBB",
1184 "MSRValue": "0x10800",
1185 "Counter": "0,1,2,3",
1186 "UMask": "0x1",
1189 "MSRIndex": "0x1a6,0x1a7",
1191 "BriefDescription": "Counts non-temporal stores",
1192 "CounterHTOff": "0,1,2,3"
1195 "EventCode": "0xB7, 0xBB",
1196 "MSRValue": "0x00010008",
1197 "Counter": "0,1,2,3",
1198 "UMask": "0x1",
1201 "MSRIndex": "0x1a6,0x1a7",
1204 "CounterHTOff": "0,1,2,3"
1207 "EventCode": "0xB7, 0xBB",
1208 "MSRValue": "0x00010001",
1209 "Counter": "0,1,2,3",
1210 "UMask": "0x1",
1213 "MSRIndex": "0x1a6,0x1a7",
1216 "CounterHTOff": "0,1,2,3"
1219 "EventCode": "0xB7, 0xBB",
1220 "MSRValue": "0x00010002",
1221 "Counter": "0,1,2,3",
1222 "UMask": "0x1",
1225 "MSRIndex": "0x1a6,0x1a7",
1228 "CounterHTOff": "0,1,2,3"
1231 "EventCode": "0xB7, 0xBB",
1232 "MSRValue": "0x00010004",
1233 "Counter": "0,1,2,3",
1234 "UMask": "0x1",
1237 "MSRIndex": "0x1a6,0x1a7",
1240 "CounterHTOff": "0,1,2,3"
1243 "EventCode": "0xB7, 0xBB",
1244 "MSRValue": "0x00010008",
1245 "Counter": "0,1,2,3",
1246 "UMask": "0x1",
1249 "MSRIndex": "0x1a6,0x1a7",
1252 "CounterHTOff": "0,1,2,3"
1255 "EventCode": "0xB7, 0xBB",
1256 "MSRValue": "0x000105B3",
1257 "Counter": "0,1,2,3",
1258 "UMask": "0x1",
1261 "MSRIndex": "0x1a6,0x1a7",
1264 "CounterHTOff": "0,1,2,3"
1267 "EventCode": "0xB7, 0xBB",
1268 "MSRValue": "0x00010122",
1269 "Counter": "0,1,2,3",
1270 "UMask": "0x1",
1273 "MSRIndex": "0x1a6,0x1a7",
1276 "CounterHTOff": "0,1,2,3"
1279 "EventCode": "0xB7, 0xBB",
1280 "MSRValue": "0x000107F7",
1281 "Counter": "0,1,2,3",
1282 "UMask": "0x1",
1285 "MSRIndex": "0x1a6,0x1a7",
1288 "CounterHTOff": "0,1,2,3"