Lines Matching +full:1 +full:- +full:5
11 "Counter": "Fixed counter 1",
16 "CounterHTOff": "Fixed counter 1"
20 "Counter": "Fixed counter 1",
22 "AnyThread": "1",
26 "CounterHTOff": "Fixed counter 1"
39 "Counter": "0,1,2,3",
43 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
44 "CounterHTOff": "0,1,2,3,4,5,6,7"
49 "Counter": "0,1,2,3",
54 "CounterHTOff": "0,1,2,3,4,5,6,7"
59 "Counter": "0,1,2,3",
64 "CounterHTOff": "0,1,2,3,4,5,6,7"
68 "Counter": "0,1,2,3",
73 "CounterMask": "1",
74 "CounterHTOff": "0,1,2,3,4,5,6,7"
78 "Counter": "0,1,2,3",
80 "EdgeDetect": "1",
84 "CounterMask": "1",
85 "CounterHTOff": "0,1,2,3,4,5,6,7"
89 "Counter": "0,1,2,3",
91 "AnyThread": "1",
95 "CounterMask": "1",
96 "CounterHTOff": "0,1,2,3,4,5,6,7"
99 …ents each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stal…
101 "Counter": "0,1,2,3",
106 "CounterHTOff": "0,1,2,3,4,5,6,7"
111 "Invert": "1",
112 "Counter": "0,1,2,3",
117 "CounterMask": "1",
118 "CounterHTOff": "0,1,2,3"
123 "Invert": "1",
124 "Counter": "0,1,2,3",
126 "AnyThread": "1",
130 "CounterMask": "1",
131 "CounterHTOff": "0,1,2,3"
134 "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.",
136 "Counter": "0,1,2,3",
140 "BriefDescription": "Number of flags-merge uops being allocated.",
141 "CounterHTOff": "0,1,2,3,4,5,6,7"
146 "Counter": "0,1,2,3",
151 "CounterHTOff": "0,1,2,3,4,5,6,7"
156 "Counter": "0,1,2,3",
161 "CounterHTOff": "0,1,2,3,4,5,6,7"
164 …": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the nu…
166 "Counter": "0,1,2,3",
171 "CounterHTOff": "0,1,2,3,4,5,6,7"
176 "Counter": "0,1,2,3",
178 "EdgeDetect": "1",
182 "CounterMask": "1",
183 "CounterHTOff": "0,1,2,3,4,5,6,7"
188 "Counter": "0,1,2,3",
193 "CounterHTOff": "0,1,2,3,4,5,6,7"
198 "Counter": "0,1,2,3",
200 "AnyThread": "1",
204 "CounterHTOff": "0,1,2,3,4,5,6,7"
209 "Counter": "0,1,2,3",
214 "CounterHTOff": "0,1,2,3,4,5,6,7"
218 "Counter": "0,1,2,3",
220 "AnyThread": "1",
224 "CounterHTOff": "0,1,2,3,4,5,6,7"
229 "Counter": "0,1,2,3",
234 "CounterHTOff": "0,1,2,3,4,5,6,7"
238 "Counter": "0,1,2,3",
240 "AnyThread": "1",
244 "CounterHTOff": "0,1,2,3,4,5,6,7"
248 "Counter": "0,1,2,3",
253 "CounterHTOff": "0,1,2,3"
257 "Counter": "0,1,2,3",
262 "CounterHTOff": "0,1,2,3,4,5,6,7"
265 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefe…
267 "Counter": "0,1,2,3",
271 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
272 "CounterHTOff": "0,1,2,3,4,5,6,7"
275 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefe…
277 "Counter": "0,1,2,3",
281 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
282 "CounterHTOff": "0,1,2,3,4,5,6,7"
286 "Counter": "0,1,2,3",
291 "CounterHTOff": "0,1,2,3,4,5,6,7"
295 "Counter": "0,1,2,3",
300 "CounterHTOff": "0,1,2,3,4,5,6,7"
304 "Counter": "0,1,2,3",
309 "CounterHTOff": "0,1,2,3,4,5,6,7"
313 "Counter": "0,1,2,3",
318 "CounterHTOff": "0,1,2,3,4,5,6,7"
323 "Counter": "0,1,2,3",
328 "CounterHTOff": "0,1,2,3,4,5,6,7"
332 "Invert": "1",
333 "Counter": "0,1,2,3",
335 "EdgeDetect": "1",
339 "CounterMask": "1",
340 "CounterHTOff": "0,1,2,3,4,5,6,7"
344 "Counter": "0,1,2,3",
349 "CounterHTOff": "0,1,2,3,4,5,6,7"
354 "Counter": "0,1,2,3",
359 "CounterHTOff": "0,1,2,3,4,5,6,7"
362 "PublicDescription": "Not taken macro-conditional branches.",
364 "Counter": "0,1,2,3",
368 "BriefDescription": "Not taken macro-conditional branches",
369 "CounterHTOff": "0,1,2,3,4,5,6,7"
372 "PublicDescription": "Taken speculative and retired macro-conditional branches.",
374 "Counter": "0,1,2,3",
378 "BriefDescription": "Taken speculative and retired macro-conditional branches",
379 "CounterHTOff": "0,1,2,3,4,5,6,7"
382 …"PublicDescription": "Taken speculative and retired macro-conditional branch instructions excludin…
384 "Counter": "0,1,2,3",
388 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
389 "CounterHTOff": "0,1,2,3,4,5,6,7"
394 "Counter": "0,1,2,3",
399 "CounterHTOff": "0,1,2,3,4,5,6,7"
404 "Counter": "0,1,2,3",
409 "CounterHTOff": "0,1,2,3,4,5,6,7"
414 "Counter": "0,1,2,3",
419 "CounterHTOff": "0,1,2,3,4,5,6,7"
424 "Counter": "0,1,2,3",
429 "CounterHTOff": "0,1,2,3,4,5,6,7"
432 "PublicDescription": "Speculative and retired macro-conditional branches.",
434 "Counter": "0,1,2,3",
438 "BriefDescription": "Speculative and retired macro-conditional branches",
439 "CounterHTOff": "0,1,2,3,4,5,6,7"
442 …"PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and ind…
444 "Counter": "0,1,2,3",
448 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
449 "CounterHTOff": "0,1,2,3,4,5,6,7"
454 "Counter": "0,1,2,3",
459 "CounterHTOff": "0,1,2,3,4,5,6,7"
463 "Counter": "0,1,2,3",
468 "CounterHTOff": "0,1,2,3,4,5,6,7"
473 "Counter": "0,1,2,3",
478 "CounterHTOff": "0,1,2,3,4,5,6,7"
483 "Counter": "0,1,2,3",
488 "CounterHTOff": "0,1,2,3,4,5,6,7"
493 "Counter": "0,1,2,3",
498 "CounterHTOff": "0,1,2,3,4,5,6,7"
503 "Counter": "0,1,2,3",
508 "CounterHTOff": "0,1,2,3,4,5,6,7"
513 "Counter": "0,1,2,3",
518 "CounterHTOff": "0,1,2,3,4,5,6,7"
523 "Counter": "0,1,2,3",
528 "CounterHTOff": "0,1,2,3,4,5,6,7"
533 "Counter": "0,1,2,3",
538 "CounterHTOff": "0,1,2,3,4,5,6,7"
543 "Counter": "0,1,2,3",
548 "CounterHTOff": "0,1,2,3,4,5,6,7"
553 "Counter": "0,1,2,3",
558 "CounterHTOff": "0,1,2,3,4,5,6,7"
563 "Counter": "0,1,2,3",
568 "CounterHTOff": "0,1,2,3,4,5,6,7"
573 "Counter": "0,1,2,3",
578 "CounterHTOff": "0,1,2,3,4,5,6,7"
583 "Counter": "0,1,2,3",
585 "AnyThread": "1",
589 "CounterHTOff": "0,1,2,3,4,5,6,7"
592 "PublicDescription": "Cycles which a Uop is dispatched on port 1.",
594 "Counter": "0,1,2,3",
598 "BriefDescription": "Cycles per thread when uops are dispatched to port 1",
599 "CounterHTOff": "0,1,2,3,4,5,6,7"
602 "PublicDescription": "Cycles per core when uops are dispatched to port 1.",
604 "Counter": "0,1,2,3",
606 "AnyThread": "1",
609 "BriefDescription": "Cycles per core when uops are dispatched to port 1",
610 "CounterHTOff": "0,1,2,3,4,5,6,7"
615 "Counter": "0,1,2,3",
620 "CounterHTOff": "0,1,2,3,4,5,6,7"
624 "Counter": "0,1,2,3",
626 "AnyThread": "1",
630 "CounterHTOff": "0,1,2,3,4,5,6,7"
635 "Counter": "0,1,2,3",
640 "CounterHTOff": "0,1,2,3,4,5,6,7"
645 "Counter": "0,1,2,3",
647 "AnyThread": "1",
651 "CounterHTOff": "0,1,2,3,4,5,6,7"
656 "Counter": "0,1,2,3",
661 "CounterHTOff": "0,1,2,3,4,5,6,7"
666 "Counter": "0,1,2,3",
668 "AnyThread": "1",
672 "CounterHTOff": "0,1,2,3,4,5,6,7"
675 "PublicDescription": "Cycles which a Uop is dispatched on port 5.",
677 "Counter": "0,1,2,3",
681 "BriefDescription": "Cycles per thread when uops are dispatched to port 5",
682 "CounterHTOff": "0,1,2,3,4,5,6,7"
685 "PublicDescription": "Cycles per core when uops are dispatched to port 5.",
687 "Counter": "0,1,2,3",
689 "AnyThread": "1",
692 "BriefDescription": "Cycles per core when uops are dispatched to port 5",
693 "CounterHTOff": "0,1,2,3,4,5,6,7"
698 "Counter": "0,1,2,3",
702 "BriefDescription": "Resource-related stall cycles",
703 "CounterHTOff": "0,1,2,3,4,5,6,7"
707 "Counter": "0,1,2,3",
712 "CounterHTOff": "0,1,2,3,4,5,6,7"
717 "Counter": "0,1,2,3",
722 "CounterHTOff": "0,1,2,3,4,5,6,7"
726 "Counter": "0,1,2,3",
730 "BriefDescription": "Cycles stalled due to re-order buffer full.",
731 "CounterHTOff": "0,1,2,3,4,5,6,7"
736 "Counter": "0,1,2,3",
741 "CounterMask": "1",
742 "CounterHTOff": "0,1,2,3,4,5,6,7"
746 "Counter": "0,1,2,3",
751 "CounterMask": "1",
752 "CounterHTOff": "0,1,2,3,4,5,6,7"
757 "Counter": "0,1,2,3",
763 "CounterHTOff": "0,1,2,3"
767 "Counter": "0,1,2,3",
773 "CounterHTOff": "0,1,2,3"
778 "Counter": "0,1,2,3",
782 …"BriefDescription": "This event increments by 1 for every cycle where there was no execute for thi…
784 "CounterHTOff": "0,1,2,3"
788 "Counter": "0,1,2,3",
794 "CounterHTOff": "0,1,2,3"
799 "Counter": "0,1,2,3",
804 "CounterMask": "5",
805 "CounterHTOff": "0,1,2,3"
809 "Counter": "0,1,2,3",
814 "CounterMask": "5",
815 "CounterHTOff": "0,1,2,3"
819 "Counter": "0,1,2,3",
825 "CounterHTOff": "0,1,2,3"
829 "Counter": "0,1,2,3",
835 "CounterHTOff": "0,1,2,3"
881 "Counter": "0,1,2,3",
886 "CounterHTOff": "0,1,2,3,4,5,6,7"
891 "Counter": "0,1,2,3",
896 "CounterMask": "1",
897 "CounterHTOff": "0,1,2,3,4,5,6,7"
902 "Counter": "0,1,2,3",
908 "CounterHTOff": "0,1,2,3,4,5,6,7"
911 …iption": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 …
913 "Counter": "0,1,2,3",
917 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
918 "CounterHTOff": "0,1,2,3,4,5,6,7"
922 "Invert": "1",
923 "Counter": "0,1,2,3",
928 "CounterMask": "1",
929 "CounterHTOff": "0,1,2,3"
932 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
934 "Counter": "0,1,2,3",
938 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
939 "CounterMask": "1",
940 "CounterHTOff": "0,1,2,3,4,5,6,7"
943 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
945 "Counter": "0,1,2,3",
949 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
951 "CounterHTOff": "0,1,2,3,4,5,6,7"
954 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
956 "Counter": "0,1,2,3",
960 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
962 "CounterHTOff": "0,1,2,3,4,5,6,7"
965 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
967 "Counter": "0,1,2,3",
971 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
973 "CounterHTOff": "0,1,2,3,4,5,6,7"
976 "PublicDescription": "Counts total number of uops to be executed per-core each cycle.",
978 "Counter": "0,1,2,3",
983 "CounterHTOff": "0,1,2,3,4,5,6,7"
986 … "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
988 "Counter": "0,1,2,3",
992 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
993 "CounterMask": "1",
994 "CounterHTOff": "0,1,2,3,4,5,6,7"
997 … "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
999 "Counter": "0,1,2,3",
1003 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
1005 "CounterHTOff": "0,1,2,3,4,5,6,7"
1008 … "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1010 "Counter": "0,1,2,3",
1014 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
1016 "CounterHTOff": "0,1,2,3,4,5,6,7"
1019 … "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1021 "Counter": "0,1,2,3",
1025 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
1027 "CounterHTOff": "0,1,2,3,4,5,6,7"
1030 "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1032 "Invert": "1",
1033 "Counter": "0,1,2,3",
1037 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",
1038 "CounterHTOff": "0,1,2,3,4,5,6,7"
1043 "Counter": "0,1,2,3",
1047 … "BriefDescription": "Number of instructions retired. General Counter - architectural event",
1048 "CounterHTOff": "0,1,2,3,4,5,6,7"
1054 "Counter": "1",
1059 "CounterHTOff": "1"
1063 "Counter": "0,1,2,3",
1068 "CounterHTOff": "0,1,2,3,4,5,6,7"
1071 "PEBS": "1",
1073 "Counter": "0,1,2,3",
1078 "CounterHTOff": "0,1,2,3,4,5,6,7"
1082 "Invert": "1",
1083 "Counter": "0,1,2,3",
1088 "CounterMask": "1",
1089 "CounterHTOff": "0,1,2,3"
1093 "Invert": "1",
1094 "Counter": "0,1,2,3",
1100 "CounterHTOff": "0,1,2,3"
1104 "Invert": "1",
1105 "Counter": "0,1,2,3",
1107 "AnyThread": "1",
1111 "CounterMask": "1",
1112 "CounterHTOff": "0,1,2,3"
1115 "PEBS": "1",
1117 "Counter": "0,1,2,3",
1122 "CounterHTOff": "0,1,2,3,4,5,6,7"
1126 "Counter": "0,1,2,3",
1128 "EdgeDetect": "1",
1132 "CounterMask": "1",
1133 "CounterHTOff": "0,1,2,3,4,5,6,7"
1136 "PublicDescription": "Number of self-modifying-code machine clears detected.",
1138 "Counter": "0,1,2,3",
1142 "BriefDescription": "Self-modifying code (SMC) detected.",
1143 "CounterHTOff": "0,1,2,3,4,5,6,7"
1148 "Counter": "0,1,2,3",
1153 "CounterHTOff": "0,1,2,3,4,5,6,7"
1158 "Counter": "0,1,2,3",
1163 "CounterHTOff": "0,1,2,3,4,5,6,7"
1166 "PEBS": "1",
1168 "Counter": "0,1,2,3",
1173 "CounterHTOff": "0,1,2,3,4,5,6,7"
1176 "PEBS": "1",
1178 "Counter": "0,1,2,3",
1183 "CounterHTOff": "0,1,2,3,4,5,6,7"
1186 "PEBS": "1",
1188 "Counter": "0,1,2,3",
1193 "CounterHTOff": "0,1,2,3,4,5,6,7"
1198 "Counter": "0,1,2,3",
1203 "CounterHTOff": "0,1,2,3"
1206 "PEBS": "1",
1208 "Counter": "0,1,2,3",
1213 "CounterHTOff": "0,1,2,3,4,5,6,7"
1218 "Counter": "0,1,2,3",
1223 "CounterHTOff": "0,1,2,3,4,5,6,7"
1226 "PEBS": "1",
1228 "Counter": "0,1,2,3",
1233 "CounterHTOff": "0,1,2,3,4,5,6,7"
1238 "Counter": "0,1,2,3",
1243 "CounterHTOff": "0,1,2,3,4,5,6,7"
1248 "Counter": "0,1,2,3",
1253 "CounterHTOff": "0,1,2,3,4,5,6,7"
1256 "PEBS": "1",
1258 "Counter": "0,1,2,3",
1263 "CounterHTOff": "0,1,2,3,4,5,6,7"
1268 "Counter": "0,1,2,3",
1273 "CounterHTOff": "0,1,2,3"
1276 "PEBS": "1",
1278 "Counter": "0,1,2,3",
1283 "CounterHTOff": "0,1,2,3,4,5,6,7"
1288 "Counter": "0,1,2,3",
1293 "CounterHTOff": "0,1,2,3,4,5,6,7"
1296 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
1298 "Counter": "0,1,2,3",
1303 "CounterHTOff": "0,1,2,3,4,5,6,7"