Lines Matching +full:0 +full:- +full:3
3 "Counter": "Fixed counter 0",
4 "UMask": "0x1",
8 "CounterHTOff": "Fixed counter 0"
12 "UMask": "0x2",
21 "UMask": "0x2",
30 "UMask": "0x3",
38 "EventCode": "0x03",
39 "Counter": "0,1,2,3",
40 "UMask": "0x2",
43 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
44 "CounterHTOff": "0,1,2,3,4,5,6,7"
48 "EventCode": "0x03",
49 "Counter": "0,1,2,3",
50 "UMask": "0x8",
54 "CounterHTOff": "0,1,2,3,4,5,6,7"
58 "EventCode": "0x07",
59 "Counter": "0,1,2,3",
60 "UMask": "0x1",
64 "CounterHTOff": "0,1,2,3,4,5,6,7"
67 "EventCode": "0x0D",
68 "Counter": "0,1,2,3",
69 "UMask": "0x3",
74 "CounterHTOff": "0,1,2,3,4,5,6,7"
77 "EventCode": "0x0D",
78 "Counter": "0,1,2,3",
79 "UMask": "0x3",
85 "CounterHTOff": "0,1,2,3,4,5,6,7"
88 "EventCode": "0x0D",
89 "Counter": "0,1,2,3",
90 "UMask": "0x3",
96 "CounterHTOff": "0,1,2,3,4,5,6,7"
100 "EventCode": "0x0E",
101 "Counter": "0,1,2,3",
102 "UMask": "0x1",
106 "CounterHTOff": "0,1,2,3,4,5,6,7"
110 "EventCode": "0x0E",
112 "Counter": "0,1,2,3",
113 "UMask": "0x1",
118 "CounterHTOff": "0,1,2,3"
122 "EventCode": "0x0E",
124 "Counter": "0,1,2,3",
125 "UMask": "0x1",
131 "CounterHTOff": "0,1,2,3"
134 "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.",
135 "EventCode": "0x0E",
136 "Counter": "0,1,2,3",
137 "UMask": "0x10",
140 "BriefDescription": "Number of flags-merge uops being allocated.",
141 "CounterHTOff": "0,1,2,3,4,5,6,7"
144 …"PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2…
145 "EventCode": "0x0E",
146 "Counter": "0,1,2,3",
147 "UMask": "0x20",
150 …w LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sour…
151 "CounterHTOff": "0,1,2,3,4,5,6,7"
155 "EventCode": "0x0E",
156 "Counter": "0,1,2,3",
157 "UMask": "0x40",
161 "CounterHTOff": "0,1,2,3,4,5,6,7"
165 "EventCode": "0x14",
166 "Counter": "0,1,2,3",
167 "UMask": "0x1",
171 "CounterHTOff": "0,1,2,3,4,5,6,7"
175 "EventCode": "0x14",
176 "Counter": "0,1,2,3",
177 "UMask": "0x4",
183 "CounterHTOff": "0,1,2,3,4,5,6,7"
187 "EventCode": "0x3C",
188 "Counter": "0,1,2,3",
189 "UMask": "0x0",
193 "CounterHTOff": "0,1,2,3,4,5,6,7"
197 "EventCode": "0x3C",
198 "Counter": "0,1,2,3",
199 "UMask": "0x0",
204 "CounterHTOff": "0,1,2,3,4,5,6,7"
208 "EventCode": "0x3C",
209 "Counter": "0,1,2,3",
210 "UMask": "0x1",
214 "CounterHTOff": "0,1,2,3,4,5,6,7"
217 "EventCode": "0x3C",
218 "Counter": "0,1,2,3",
219 "UMask": "0x1",
224 "CounterHTOff": "0,1,2,3,4,5,6,7"
228 "EventCode": "0x3C",
229 "Counter": "0,1,2,3",
230 "UMask": "0x1",
234 "CounterHTOff": "0,1,2,3,4,5,6,7"
237 "EventCode": "0x3C",
238 "Counter": "0,1,2,3",
239 "UMask": "0x1",
244 "CounterHTOff": "0,1,2,3,4,5,6,7"
247 "EventCode": "0x3C",
248 "Counter": "0,1,2,3",
249 "UMask": "0x2",
253 "CounterHTOff": "0,1,2,3"
256 "EventCode": "0x3C",
257 "Counter": "0,1,2,3",
258 "UMask": "0x2",
262 "CounterHTOff": "0,1,2,3,4,5,6,7"
265 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefe…
266 "EventCode": "0x4C",
267 "Counter": "0,1,2,3",
268 "UMask": "0x1",
271 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
272 "CounterHTOff": "0,1,2,3,4,5,6,7"
275 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefe…
276 "EventCode": "0x4C",
277 "Counter": "0,1,2,3",
278 "UMask": "0x2",
281 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
282 "CounterHTOff": "0,1,2,3,4,5,6,7"
285 "EventCode": "0x58",
286 "Counter": "0,1,2,3",
287 "UMask": "0x1",
291 "CounterHTOff": "0,1,2,3,4,5,6,7"
294 "EventCode": "0x58",
295 "Counter": "0,1,2,3",
296 "UMask": "0x2",
300 "CounterHTOff": "0,1,2,3,4,5,6,7"
303 "EventCode": "0x58",
304 "Counter": "0,1,2,3",
305 "UMask": "0x4",
309 "CounterHTOff": "0,1,2,3,4,5,6,7"
312 "EventCode": "0x58",
313 "Counter": "0,1,2,3",
314 "UMask": "0x8",
318 "CounterHTOff": "0,1,2,3,4,5,6,7"
322 "EventCode": "0x5E",
323 "Counter": "0,1,2,3",
324 "UMask": "0x1",
328 "CounterHTOff": "0,1,2,3,4,5,6,7"
331 "EventCode": "0x5E",
333 "Counter": "0,1,2,3",
334 "UMask": "0x1",
340 "CounterHTOff": "0,1,2,3,4,5,6,7"
343 "EventCode": "0x87",
344 "Counter": "0,1,2,3",
345 "UMask": "0x1",
349 "CounterHTOff": "0,1,2,3,4,5,6,7"
353 "EventCode": "0x87",
354 "Counter": "0,1,2,3",
355 "UMask": "0x4",
359 "CounterHTOff": "0,1,2,3,4,5,6,7"
362 "PublicDescription": "Not taken macro-conditional branches.",
363 "EventCode": "0x88",
364 "Counter": "0,1,2,3",
365 "UMask": "0x41",
368 "BriefDescription": "Not taken macro-conditional branches",
369 "CounterHTOff": "0,1,2,3,4,5,6,7"
372 "PublicDescription": "Taken speculative and retired macro-conditional branches.",
373 "EventCode": "0x88",
374 "Counter": "0,1,2,3",
375 "UMask": "0x81",
378 "BriefDescription": "Taken speculative and retired macro-conditional branches",
379 "CounterHTOff": "0,1,2,3,4,5,6,7"
382 …"PublicDescription": "Taken speculative and retired macro-conditional branch instructions excludin…
383 "EventCode": "0x88",
384 "Counter": "0,1,2,3",
385 "UMask": "0x82",
388 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
389 "CounterHTOff": "0,1,2,3,4,5,6,7"
393 "EventCode": "0x88",
394 "Counter": "0,1,2,3",
395 "UMask": "0x84",
399 "CounterHTOff": "0,1,2,3,4,5,6,7"
403 "EventCode": "0x88",
404 "Counter": "0,1,2,3",
405 "UMask": "0x88",
409 "CounterHTOff": "0,1,2,3,4,5,6,7"
413 "EventCode": "0x88",
414 "Counter": "0,1,2,3",
415 "UMask": "0x90",
419 "CounterHTOff": "0,1,2,3,4,5,6,7"
423 "EventCode": "0x88",
424 "Counter": "0,1,2,3",
425 "UMask": "0xa0",
429 "CounterHTOff": "0,1,2,3,4,5,6,7"
432 "PublicDescription": "Speculative and retired macro-conditional branches.",
433 "EventCode": "0x88",
434 "Counter": "0,1,2,3",
435 "UMask": "0xc1",
438 "BriefDescription": "Speculative and retired macro-conditional branches",
439 "CounterHTOff": "0,1,2,3,4,5,6,7"
442 …"PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and ind…
443 "EventCode": "0x88",
444 "Counter": "0,1,2,3",
445 "UMask": "0xc2",
448 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
449 "CounterHTOff": "0,1,2,3,4,5,6,7"
453 "EventCode": "0x88",
454 "Counter": "0,1,2,3",
455 "UMask": "0xc4",
459 "CounterHTOff": "0,1,2,3,4,5,6,7"
462 "EventCode": "0x88",
463 "Counter": "0,1,2,3",
464 "UMask": "0xc8",
468 "CounterHTOff": "0,1,2,3,4,5,6,7"
472 "EventCode": "0x88",
473 "Counter": "0,1,2,3",
474 "UMask": "0xd0",
478 "CounterHTOff": "0,1,2,3,4,5,6,7"
482 "EventCode": "0x88",
483 "Counter": "0,1,2,3",
484 "UMask": "0xff",
488 "CounterHTOff": "0,1,2,3,4,5,6,7"
492 "EventCode": "0x89",
493 "Counter": "0,1,2,3",
494 "UMask": "0x41",
498 "CounterHTOff": "0,1,2,3,4,5,6,7"
502 "EventCode": "0x89",
503 "Counter": "0,1,2,3",
504 "UMask": "0x81",
508 "CounterHTOff": "0,1,2,3,4,5,6,7"
512 "EventCode": "0x89",
513 "Counter": "0,1,2,3",
514 "UMask": "0x84",
518 "CounterHTOff": "0,1,2,3,4,5,6,7"
522 "EventCode": "0x89",
523 "Counter": "0,1,2,3",
524 "UMask": "0x88",
528 "CounterHTOff": "0,1,2,3,4,5,6,7"
532 "EventCode": "0x89",
533 "Counter": "0,1,2,3",
534 "UMask": "0xa0",
538 "CounterHTOff": "0,1,2,3,4,5,6,7"
542 "EventCode": "0x89",
543 "Counter": "0,1,2,3",
544 "UMask": "0xc1",
548 "CounterHTOff": "0,1,2,3,4,5,6,7"
552 "EventCode": "0x89",
553 "Counter": "0,1,2,3",
554 "UMask": "0xc4",
558 "CounterHTOff": "0,1,2,3,4,5,6,7"
562 "EventCode": "0x89",
563 "Counter": "0,1,2,3",
564 "UMask": "0xff",
568 "CounterHTOff": "0,1,2,3,4,5,6,7"
571 "PublicDescription": "Cycles which a Uop is dispatched on port 0.",
572 "EventCode": "0xA1",
573 "Counter": "0,1,2,3",
574 "UMask": "0x1",
577 "BriefDescription": "Cycles per thread when uops are dispatched to port 0",
578 "CounterHTOff": "0,1,2,3,4,5,6,7"
581 "PublicDescription": "Cycles per core when uops are dispatched to port 0.",
582 "EventCode": "0xA1",
583 "Counter": "0,1,2,3",
584 "UMask": "0x1",
588 "BriefDescription": "Cycles per core when uops are dispatched to port 0",
589 "CounterHTOff": "0,1,2,3,4,5,6,7"
593 "EventCode": "0xA1",
594 "Counter": "0,1,2,3",
595 "UMask": "0x2",
599 "CounterHTOff": "0,1,2,3,4,5,6,7"
603 "EventCode": "0xA1",
604 "Counter": "0,1,2,3",
605 "UMask": "0x2",
610 "CounterHTOff": "0,1,2,3,4,5,6,7"
614 "EventCode": "0xA1",
615 "Counter": "0,1,2,3",
616 "UMask": "0xc",
620 "CounterHTOff": "0,1,2,3,4,5,6,7"
623 "EventCode": "0xA1",
624 "Counter": "0,1,2,3",
625 "UMask": "0xc",
630 "CounterHTOff": "0,1,2,3,4,5,6,7"
633 "PublicDescription": "Cycles which a Uop is dispatched on port 3.",
634 "EventCode": "0xA1",
635 "Counter": "0,1,2,3",
636 "UMask": "0x30",
639 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3",
640 "CounterHTOff": "0,1,2,3,4,5,6,7"
643 "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
644 "EventCode": "0xA1",
645 "Counter": "0,1,2,3",
646 "UMask": "0x30",
650 "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3",
651 "CounterHTOff": "0,1,2,3,4,5,6,7"
655 "EventCode": "0xA1",
656 "Counter": "0,1,2,3",
657 "UMask": "0x40",
661 "CounterHTOff": "0,1,2,3,4,5,6,7"
665 "EventCode": "0xA1",
666 "Counter": "0,1,2,3",
667 "UMask": "0x40",
672 "CounterHTOff": "0,1,2,3,4,5,6,7"
676 "EventCode": "0xA1",
677 "Counter": "0,1,2,3",
678 "UMask": "0x80",
682 "CounterHTOff": "0,1,2,3,4,5,6,7"
686 "EventCode": "0xA1",
687 "Counter": "0,1,2,3",
688 "UMask": "0x80",
693 "CounterHTOff": "0,1,2,3,4,5,6,7"
697 "EventCode": "0xA2",
698 "Counter": "0,1,2,3",
699 "UMask": "0x1",
702 "BriefDescription": "Resource-related stall cycles",
703 "CounterHTOff": "0,1,2,3,4,5,6,7"
706 "EventCode": "0xA2",
707 "Counter": "0,1,2,3",
708 "UMask": "0x4",
712 "CounterHTOff": "0,1,2,3,4,5,6,7"
716 "EventCode": "0xA2",
717 "Counter": "0,1,2,3",
718 "UMask": "0x8",
722 "CounterHTOff": "0,1,2,3,4,5,6,7"
725 "EventCode": "0xA2",
726 "Counter": "0,1,2,3",
727 "UMask": "0x10",
730 "BriefDescription": "Cycles stalled due to re-order buffer full.",
731 "CounterHTOff": "0,1,2,3,4,5,6,7"
735 "EventCode": "0xA3",
736 "Counter": "0,1,2,3",
737 "UMask": "0x1",
742 "CounterHTOff": "0,1,2,3,4,5,6,7"
745 "EventCode": "0xA3",
746 "Counter": "0,1,2,3",
747 "UMask": "0x1",
752 "CounterHTOff": "0,1,2,3,4,5,6,7"
756 "EventCode": "0xA3",
757 "Counter": "0,1,2,3",
758 "UMask": "0x2",
763 "CounterHTOff": "0,1,2,3"
766 "EventCode": "0xA3",
767 "Counter": "0,1,2,3",
768 "UMask": "0x2",
773 "CounterHTOff": "0,1,2,3"
777 "EventCode": "0xA3",
778 "Counter": "0,1,2,3",
779 "UMask": "0x4",
784 "CounterHTOff": "0,1,2,3"
787 "EventCode": "0xA3",
788 "Counter": "0,1,2,3",
789 "UMask": "0x4",
794 "CounterHTOff": "0,1,2,3"
798 "EventCode": "0xA3",
799 "Counter": "0,1,2,3",
800 "UMask": "0x5",
805 "CounterHTOff": "0,1,2,3"
808 "EventCode": "0xA3",
809 "Counter": "0,1,2,3",
810 "UMask": "0x5",
815 "CounterHTOff": "0,1,2,3"
818 "EventCode": "0xA3",
819 "Counter": "0,1,2,3",
820 "UMask": "0x6",
825 "CounterHTOff": "0,1,2,3"
828 "EventCode": "0xA3",
829 "Counter": "0,1,2,3",
830 "UMask": "0x6",
835 "CounterHTOff": "0,1,2,3"
839 "EventCode": "0xA3",
841 "UMask": "0x8",
849 "EventCode": "0xA3",
851 "UMask": "0x8",
859 "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.",
860 "EventCode": "0xA3",
862 "UMask": "0xc",
870 "EventCode": "0xA3",
872 "UMask": "0xc",
880 "EventCode": "0xA8",
881 "Counter": "0,1,2,3",
882 "UMask": "0x1",
886 "CounterHTOff": "0,1,2,3,4,5,6,7"
890 "EventCode": "0xA8",
891 "Counter": "0,1,2,3",
892 "UMask": "0x1",
897 "CounterHTOff": "0,1,2,3,4,5,6,7"
901 "EventCode": "0xA8",
902 "Counter": "0,1,2,3",
903 "UMask": "0x1",
908 "CounterHTOff": "0,1,2,3,4,5,6,7"
911 …"PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask …
912 "EventCode": "0xB1",
913 "Counter": "0,1,2,3",
914 "UMask": "0x1",
917 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
918 "CounterHTOff": "0,1,2,3,4,5,6,7"
921 "EventCode": "0xB1",
923 "Counter": "0,1,2,3",
924 "UMask": "0x1",
929 "CounterHTOff": "0,1,2,3"
932 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
933 "EventCode": "0xB1",
934 "Counter": "0,1,2,3",
935 "UMask": "0x1",
938 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
940 "CounterHTOff": "0,1,2,3,4,5,6,7"
943 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
944 "EventCode": "0xB1",
945 "Counter": "0,1,2,3",
946 "UMask": "0x1",
949 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
951 "CounterHTOff": "0,1,2,3,4,5,6,7"
954 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
955 "EventCode": "0xB1",
956 "Counter": "0,1,2,3",
957 "UMask": "0x1",
960 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
961 "CounterMask": "3",
962 "CounterHTOff": "0,1,2,3,4,5,6,7"
965 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
966 "EventCode": "0xB1",
967 "Counter": "0,1,2,3",
968 "UMask": "0x1",
971 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
973 "CounterHTOff": "0,1,2,3,4,5,6,7"
976 "PublicDescription": "Counts total number of uops to be executed per-core each cycle.",
977 "EventCode": "0xB1",
978 "Counter": "0,1,2,3",
979 "UMask": "0x2",
983 "CounterHTOff": "0,1,2,3,4,5,6,7"
986 … "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
987 "EventCode": "0xB1",
988 "Counter": "0,1,2,3",
989 "UMask": "0x2",
992 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
994 "CounterHTOff": "0,1,2,3,4,5,6,7"
997 … "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
998 "EventCode": "0xB1",
999 "Counter": "0,1,2,3",
1000 "UMask": "0x2",
1003 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
1005 "CounterHTOff": "0,1,2,3,4,5,6,7"
1008 … "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1009 "EventCode": "0xB1",
1010 "Counter": "0,1,2,3",
1011 "UMask": "0x2",
1014 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
1015 "CounterMask": "3",
1016 "CounterHTOff": "0,1,2,3,4,5,6,7"
1019 … "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1020 "EventCode": "0xB1",
1021 "Counter": "0,1,2,3",
1022 "UMask": "0x2",
1025 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
1027 "CounterHTOff": "0,1,2,3,4,5,6,7"
1030 "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1031 "EventCode": "0xB1",
1033 "Counter": "0,1,2,3",
1034 "UMask": "0x2",
1037 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",
1038 "CounterHTOff": "0,1,2,3,4,5,6,7"
1042 "EventCode": "0xC0",
1043 "Counter": "0,1,2,3",
1044 "UMask": "0x0",
1047 … "BriefDescription": "Number of instructions retired. General Counter - architectural event",
1048 "CounterHTOff": "0,1,2,3,4,5,6,7"
1053 "EventCode": "0xC0",
1055 "UMask": "0x1",
1062 "EventCode": "0xC1",
1063 "Counter": "0,1,2,3",
1064 "UMask": "0x80",
1068 "CounterHTOff": "0,1,2,3,4,5,6,7"
1072 "EventCode": "0xC2",
1073 "Counter": "0,1,2,3",
1074 "UMask": "0x1",
1078 "CounterHTOff": "0,1,2,3,4,5,6,7"
1081 "EventCode": "0xC2",
1083 "Counter": "0,1,2,3",
1084 "UMask": "0x1",
1089 "CounterHTOff": "0,1,2,3"
1092 "EventCode": "0xC2",
1094 "Counter": "0,1,2,3",
1095 "UMask": "0x1",
1100 "CounterHTOff": "0,1,2,3"
1103 "EventCode": "0xC2",
1105 "Counter": "0,1,2,3",
1106 "UMask": "0x1",
1112 "CounterHTOff": "0,1,2,3"
1116 "EventCode": "0xC2",
1117 "Counter": "0,1,2,3",
1118 "UMask": "0x2",
1122 "CounterHTOff": "0,1,2,3,4,5,6,7"
1125 "EventCode": "0xC3",
1126 "Counter": "0,1,2,3",
1127 "UMask": "0x1",
1133 "CounterHTOff": "0,1,2,3,4,5,6,7"
1136 "PublicDescription": "Number of self-modifying-code machine clears detected.",
1137 "EventCode": "0xC3",
1138 "Counter": "0,1,2,3",
1139 "UMask": "0x4",
1142 "BriefDescription": "Self-modifying code (SMC) detected.",
1143 "CounterHTOff": "0,1,2,3,4,5,6,7"
1146 …ed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
1147 "EventCode": "0xC3",
1148 "Counter": "0,1,2,3",
1149 "UMask": "0x20",
1152 …el AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
1153 "CounterHTOff": "0,1,2,3,4,5,6,7"
1157 "EventCode": "0xC4",
1158 "Counter": "0,1,2,3",
1159 "UMask": "0x0",
1163 "CounterHTOff": "0,1,2,3,4,5,6,7"
1167 "EventCode": "0xC4",
1168 "Counter": "0,1,2,3",
1169 "UMask": "0x1",
1173 "CounterHTOff": "0,1,2,3,4,5,6,7"
1177 "EventCode": "0xC4",
1178 "Counter": "0,1,2,3",
1179 "UMask": "0x2",
1183 "CounterHTOff": "0,1,2,3,4,5,6,7"
1187 "EventCode": "0xC4",
1188 "Counter": "0,1,2,3",
1189 "UMask": "0x2",
1192 …riefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
1193 "CounterHTOff": "0,1,2,3,4,5,6,7"
1197 "EventCode": "0xC4",
1198 "Counter": "0,1,2,3",
1199 "UMask": "0x4",
1203 "CounterHTOff": "0,1,2,3"
1207 "EventCode": "0xC4",
1208 "Counter": "0,1,2,3",
1209 "UMask": "0x8",
1213 "CounterHTOff": "0,1,2,3,4,5,6,7"
1217 "EventCode": "0xC4",
1218 "Counter": "0,1,2,3",
1219 "UMask": "0x10",
1223 "CounterHTOff": "0,1,2,3,4,5,6,7"
1227 "EventCode": "0xC4",
1228 "Counter": "0,1,2,3",
1229 "UMask": "0x20",
1233 "CounterHTOff": "0,1,2,3,4,5,6,7"
1237 "EventCode": "0xC4",
1238 "Counter": "0,1,2,3",
1239 "UMask": "0x40",
1243 "CounterHTOff": "0,1,2,3,4,5,6,7"
1247 "EventCode": "0xC5",
1248 "Counter": "0,1,2,3",
1249 "UMask": "0x0",
1253 "CounterHTOff": "0,1,2,3,4,5,6,7"
1257 "EventCode": "0xC5",
1258 "Counter": "0,1,2,3",
1259 "UMask": "0x1",
1263 "CounterHTOff": "0,1,2,3,4,5,6,7"
1267 "EventCode": "0xC5",
1268 "Counter": "0,1,2,3",
1269 "UMask": "0x4",
1273 "CounterHTOff": "0,1,2,3"
1277 "EventCode": "0xC5",
1278 "Counter": "0,1,2,3",
1279 "UMask": "0x20",
1283 "CounterHTOff": "0,1,2,3,4,5,6,7"
1287 "EventCode": "0xCC",
1288 "Counter": "0,1,2,3",
1289 "UMask": "0x20",
1293 "CounterHTOff": "0,1,2,3,4,5,6,7"
1296 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
1297 "EventCode": "0xE6",
1298 "Counter": "0,1,2,3",
1299 "UMask": "0x1f",
1303 "CounterHTOff": "0,1,2,3,4,5,6,7"