Lines Matching +full:per +full:- +full:port
43 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
134 "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.",
140 "BriefDescription": "Number of flags-merge uops being allocated.",
265 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefe…
271 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
275 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefe…
281 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
362 "PublicDescription": "Not taken macro-conditional branches.",
368 "BriefDescription": "Not taken macro-conditional branches",
372 "PublicDescription": "Taken speculative and retired macro-conditional branches.",
378 "BriefDescription": "Taken speculative and retired macro-conditional branches",
382 …"PublicDescription": "Taken speculative and retired macro-conditional branch instructions excludin…
388 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
432 "PublicDescription": "Speculative and retired macro-conditional branches.",
438 "BriefDescription": "Speculative and retired macro-conditional branches",
442 …"PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and ind…
448 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
571 "PublicDescription": "Cycles which a Uop is dispatched on port 0.",
577 "BriefDescription": "Cycles per thread when uops are dispatched to port 0",
581 "PublicDescription": "Cycles per core when uops are dispatched to port 0.",
588 "BriefDescription": "Cycles per core when uops are dispatched to port 0",
592 "PublicDescription": "Cycles which a Uop is dispatched on port 1.",
598 "BriefDescription": "Cycles per thread when uops are dispatched to port 1",
602 "PublicDescription": "Cycles per core when uops are dispatched to port 1.",
609 "BriefDescription": "Cycles per core when uops are dispatched to port 1",
613 "PublicDescription": "Cycles which a Uop is dispatched on port 2.",
619 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2",
629 …"BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired…
633 "PublicDescription": "Cycles which a Uop is dispatched on port 3.",
639 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3",
643 "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
650 "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3",
654 "PublicDescription": "Cycles which a Uop is dispatched on port 4.",
660 "BriefDescription": "Cycles per thread when uops are dispatched to port 4",
664 "PublicDescription": "Cycles per core when uops are dispatched to port 4.",
671 "BriefDescription": "Cycles per core when uops are dispatched to port 4",
675 "PublicDescription": "Cycles which a Uop is dispatched on port 5.",
681 "BriefDescription": "Cycles per thread when uops are dispatched to port 5",
685 "PublicDescription": "Cycles per core when uops are dispatched to port 5.",
692 "BriefDescription": "Cycles per core when uops are dispatched to port 5",
702 "BriefDescription": "Resource-related stall cycles",
730 "BriefDescription": "Cycles stalled due to re-order buffer full.",
734 "PublicDescription": "Cycles with pending L2 miss loads. Set AnyThread to count per core.",
755 "PublicDescription": "Cycles with pending memory loads. Set AnyThread to count per core.",
838 … "PublicDescription": "Cycles with pending L1 cache miss loads. Set AnyThread to count per core.",
911 …"PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask …
917 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
932 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
938 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
943 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
949 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
954 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
960 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
965 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
971 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
976 "PublicDescription": "Counts total number of uops to be executed per-core each cycle.",
986 … "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
992 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
997 … "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1003 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
1008 … "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1014 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
1019 … "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1025 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
1030 "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1037 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",
1047 … "BriefDescription": "Number of instructions retired. General Counter - architectural event",
1136 "PublicDescription": "Number of self-modifying-code machine clears detected.",
1142 "BriefDescription": "Self-modifying code (SMC) detected.",
1296 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",