Lines Matching +full:0 +full:- +full:3
3 "UMask": "0x1",
5 "Counter": "Fixed counter 0",
8 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
10 "CounterHTOff": "Fixed counter 0"
13 "UMask": "0x2",
22 "UMask": "0x2",
31 "UMask": "0x3",
40 "EventCode": "0x03",
41 "UMask": "0x2",
43 "Counter": "0,1,2,3",
47 "CounterHTOff": "0,1,2,3,4,5,6,7"
50 "EventCode": "0x03",
51 "UMask": "0x8",
53 "Counter": "0,1,2,3",
57 "CounterHTOff": "0,1,2,3,4,5,6,7"
60 "EventCode": "0x07",
61 "UMask": "0x1",
63 "Counter": "0,1,2,3",
67 "CounterHTOff": "0,1,2,3,4,5,6,7"
70 "EventCode": "0x0D",
71 "UMask": "0x3",
73 "Counter": "0,1,2,3",
78 "CounterHTOff": "0,1,2,3,4,5,6,7"
81 "EventCode": "0x0D",
82 "UMask": "0x3",
84 "Counter": "0,1,2,3",
90 "CounterHTOff": "0,1,2,3,4,5,6,7"
93 "EventCode": "0x0E",
94 "UMask": "0x1",
96 "Counter": "0,1,2,3",
98 …ued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stag…
100 "CounterHTOff": "0,1,2,3,4,5,6,7"
104 "EventCode": "0x0E",
105 "UMask": "0x1",
107 "Counter": "0,1,2,3",
111 "CounterHTOff": "0,1,2,3"
115 "EventCode": "0x0E",
116 "UMask": "0x1",
118 "Counter": "0,1,2,3",
123 "CounterHTOff": "0,1,2,3"
126 "EventCode": "0x0E",
127 "UMask": "0x10",
128 …"BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensiti…
129 "Counter": "0,1,2,3",
131 "PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.",
133 "CounterHTOff": "0,1,2,3,4,5,6,7"
136 "EventCode": "0x0E",
137 "UMask": "0x20",
138 …w LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sour…
139 "Counter": "0,1,2,3",
141 …"PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (for ex…
143 "CounterHTOff": "0,1,2,3,4,5,6,7"
146 "EventCode": "0x0E",
147 "UMask": "0x40",
149 "Counter": "0,1,2,3",
153 "CounterHTOff": "0,1,2,3,4,5,6,7"
156 "EventCode": "0x14",
157 "UMask": "0x2",
159 "Counter": "0,1,2,3",
162 "CounterHTOff": "0,1,2,3,4,5,6,7"
165 "EventCode": "0x3C",
166 "UMask": "0x0",
168 "Counter": "0,1,2,3",
172 "CounterHTOff": "0,1,2,3,4,5,6,7"
175 "EventCode": "0x3C",
176 "UMask": "0x0",
178 "Counter": "0,1,2,3",
182 "CounterHTOff": "0,1,2,3,4,5,6,7"
185 "EventCode": "0x3C",
186 "UMask": "0x1",
188 "Counter": "0,1,2,3",
192 "CounterHTOff": "0,1,2,3,4,5,6,7"
195 "EventCode": "0x3C",
196 "UMask": "0x1",
198 "Counter": "0,1,2,3",
203 "CounterHTOff": "0,1,2,3,4,5,6,7"
206 "EventCode": "0x3C",
207 "UMask": "0x1",
209 "Counter": "0,1,2,3",
213 "CounterHTOff": "0,1,2,3,4,5,6,7"
216 "EventCode": "0x3C",
217 "UMask": "0x1",
219 "Counter": "0,1,2,3",
224 "CounterHTOff": "0,1,2,3,4,5,6,7"
227 "EventCode": "0x3c",
228 "UMask": "0x2",
230 "Counter": "0,1,2,3",
233 "CounterHTOff": "0,1,2,3"
236 "EventCode": "0x3C",
237 "UMask": "0x2",
239 "Counter": "0,1,2,3",
242 "CounterHTOff": "0,1,2,3,4,5,6,7"
245 "EventCode": "0x4c",
246 "UMask": "0x1",
247 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
248 "Counter": "0,1,2,3",
250 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefe…
252 "CounterHTOff": "0,1,2,3,4,5,6,7"
255 "EventCode": "0x4c",
256 "UMask": "0x2",
257 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
258 "Counter": "0,1,2,3",
260 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefe…
262 "CounterHTOff": "0,1,2,3,4,5,6,7"
265 "EventCode": "0x58",
266 "UMask": "0x1",
268 "Counter": "0,1,2,3",
272 "CounterHTOff": "0,1,2,3,4,5,6,7"
275 "EventCode": "0x58",
276 "UMask": "0x2",
278 "Counter": "0,1,2,3",
282 "CounterHTOff": "0,1,2,3,4,5,6,7"
285 "EventCode": "0x58",
286 "UMask": "0x4",
288 "Counter": "0,1,2,3",
292 "CounterHTOff": "0,1,2,3,4,5,6,7"
295 "EventCode": "0x58",
296 "UMask": "0x8",
298 "Counter": "0,1,2,3",
302 "CounterHTOff": "0,1,2,3,4,5,6,7"
305 "EventCode": "0x5E",
306 "UMask": "0x1",
308 "Counter": "0,1,2,3",
310 …micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an u…
312 "CounterHTOff": "0,1,2,3,4,5,6,7"
317 "EventCode": "0x5E",
318 "UMask": "0x1",
320 "Counter": "0,1,2,3",
324 "CounterHTOff": "0,1,2,3,4,5,6,7"
327 "EventCode": "0x87",
328 "UMask": "0x1",
330 "Counter": "0,1,2,3",
334 "CounterHTOff": "0,1,2,3,4,5,6,7"
337 "EventCode": "0x87",
338 "UMask": "0x4",
340 "Counter": "0,1,2,3",
344 "CounterHTOff": "0,1,2,3,4,5,6,7"
347 "EventCode": "0x88",
348 "UMask": "0x41",
349 "BriefDescription": "Not taken macro-conditional branches.",
350 "Counter": "0,1,2,3",
353 "CounterHTOff": "0,1,2,3,4,5,6,7"
356 "EventCode": "0x88",
357 "UMask": "0x81",
358 "BriefDescription": "Taken speculative and retired macro-conditional branches.",
359 "Counter": "0,1,2,3",
362 "CounterHTOff": "0,1,2,3,4,5,6,7"
365 "EventCode": "0x88",
366 "UMask": "0x82",
367 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
368 "Counter": "0,1,2,3",
371 "CounterHTOff": "0,1,2,3,4,5,6,7"
374 "EventCode": "0x88",
375 "UMask": "0x84",
377 "Counter": "0,1,2,3",
380 "CounterHTOff": "0,1,2,3,4,5,6,7"
383 "EventCode": "0x88",
384 "UMask": "0x88",
386 "Counter": "0,1,2,3",
389 "CounterHTOff": "0,1,2,3,4,5,6,7"
392 "EventCode": "0x88",
393 "UMask": "0x90",
395 "Counter": "0,1,2,3",
398 "CounterHTOff": "0,1,2,3,4,5,6,7"
401 "EventCode": "0x88",
402 "UMask": "0xa0",
404 "Counter": "0,1,2,3",
407 "CounterHTOff": "0,1,2,3,4,5,6,7"
410 "EventCode": "0x88",
411 "UMask": "0xc1",
412 "BriefDescription": "Speculative and retired macro-conditional branches.",
413 "Counter": "0,1,2,3",
416 "CounterHTOff": "0,1,2,3,4,5,6,7"
419 "EventCode": "0x88",
420 "UMask": "0xc2",
421 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
422 "Counter": "0,1,2,3",
425 "CounterHTOff": "0,1,2,3,4,5,6,7"
428 "EventCode": "0x88",
429 "UMask": "0xc4",
431 "Counter": "0,1,2,3",
434 "CounterHTOff": "0,1,2,3,4,5,6,7"
437 "EventCode": "0x88",
438 "UMask": "0xc8",
440 "Counter": "0,1,2,3",
443 "CounterHTOff": "0,1,2,3,4,5,6,7"
446 "EventCode": "0x88",
447 "UMask": "0xd0",
449 "Counter": "0,1,2,3",
452 "CounterHTOff": "0,1,2,3,4,5,6,7"
455 "EventCode": "0x88",
456 "UMask": "0xff",
458 "Counter": "0,1,2,3",
462 "CounterHTOff": "0,1,2,3,4,5,6,7"
465 "EventCode": "0x89",
466 "UMask": "0x41",
468 "Counter": "0,1,2,3",
471 "CounterHTOff": "0,1,2,3,4,5,6,7"
474 "EventCode": "0x89",
475 "UMask": "0x81",
477 "Counter": "0,1,2,3",
480 "CounterHTOff": "0,1,2,3,4,5,6,7"
483 "EventCode": "0x89",
484 "UMask": "0x84",
486 "Counter": "0,1,2,3",
489 "CounterHTOff": "0,1,2,3,4,5,6,7"
492 "EventCode": "0x89",
493 "UMask": "0x88",
495 "Counter": "0,1,2,3",
498 "CounterHTOff": "0,1,2,3,4,5,6,7"
501 "EventCode": "0x89",
502 "UMask": "0xa0",
504 "Counter": "0,1,2,3",
507 "CounterHTOff": "0,1,2,3,4,5,6,7"
510 "EventCode": "0x89",
511 "UMask": "0xc1",
513 "Counter": "0,1,2,3",
516 "CounterHTOff": "0,1,2,3,4,5,6,7"
519 "EventCode": "0x89",
520 "UMask": "0xc4",
522 "Counter": "0,1,2,3",
525 "CounterHTOff": "0,1,2,3,4,5,6,7"
528 "EventCode": "0x89",
529 "UMask": "0xff",
531 "Counter": "0,1,2,3",
535 "CounterHTOff": "0,1,2,3,4,5,6,7"
538 "EventCode": "0xA1",
539 "UMask": "0x1",
540 "BriefDescription": "Cycles per thread when uops are executed in port 0",
541 "Counter": "0,1,2,3",
543 "PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.",
545 "CounterHTOff": "0,1,2,3,4,5,6,7"
548 "EventCode": "0xA1",
549 "UMask": "0x1",
550 "BriefDescription": "Cycles per core when uops are executed in port 0.",
551 "Counter": "0,1,2,3",
554 "PublicDescription": "Cycles per core when uops are exectuted in port 0.",
556 "CounterHTOff": "0,1,2,3,4,5,6,7"
559 "EventCode": "0xA1",
560 "UMask": "0x1",
561 "BriefDescription": "Cycles per thread when uops are executed in port 0.",
562 "Counter": "0,1,2,3",
565 "CounterHTOff": "0,1,2,3,4,5,6,7"
568 "EventCode": "0xA1",
569 "UMask": "0x2",
571 "Counter": "0,1,2,3",
575 "CounterHTOff": "0,1,2,3,4,5,6,7"
578 "EventCode": "0xA1",
579 "UMask": "0x2",
581 "Counter": "0,1,2,3",
586 "CounterHTOff": "0,1,2,3,4,5,6,7"
589 "EventCode": "0xA1",
590 "UMask": "0x2",
592 "Counter": "0,1,2,3",
595 "CounterHTOff": "0,1,2,3,4,5,6,7"
598 "EventCode": "0xA1",
599 "UMask": "0x4",
601 "Counter": "0,1,2,3",
605 "CounterHTOff": "0,1,2,3,4,5,6,7"
608 "EventCode": "0xA1",
609 "UMask": "0x4",
611 "Counter": "0,1,2,3",
615 "CounterHTOff": "0,1,2,3,4,5,6,7"
618 "EventCode": "0xA1",
619 "UMask": "0x4",
621 "Counter": "0,1,2,3",
624 "CounterHTOff": "0,1,2,3,4,5,6,7"
627 "EventCode": "0xA1",
628 "UMask": "0x8",
629 "BriefDescription": "Cycles per thread when uops are executed in port 3",
630 "Counter": "0,1,2,3",
632 "PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.",
634 "CounterHTOff": "0,1,2,3,4,5,6,7"
637 "EventCode": "0xA1",
638 "UMask": "0x8",
639 "BriefDescription": "Cycles per core when uops are dispatched to port 3.",
640 "Counter": "0,1,2,3",
644 "CounterHTOff": "0,1,2,3,4,5,6,7"
647 "EventCode": "0xA1",
648 "UMask": "0x8",
649 "BriefDescription": "Cycles per thread when uops are executed in port 3.",
650 "Counter": "0,1,2,3",
653 "CounterHTOff": "0,1,2,3,4,5,6,7"
656 "EventCode": "0xA1",
657 "UMask": "0x10",
659 "Counter": "0,1,2,3",
663 "CounterHTOff": "0,1,2,3,4,5,6,7"
666 "EventCode": "0xA1",
667 "UMask": "0x10",
669 "Counter": "0,1,2,3",
674 "CounterHTOff": "0,1,2,3,4,5,6,7"
677 "EventCode": "0xA1",
678 "UMask": "0x10",
680 "Counter": "0,1,2,3",
683 "CounterHTOff": "0,1,2,3,4,5,6,7"
686 "EventCode": "0xA1",
687 "UMask": "0x20",
689 "Counter": "0,1,2,3",
693 "CounterHTOff": "0,1,2,3,4,5,6,7"
696 "EventCode": "0xA1",
697 "UMask": "0x20",
699 "Counter": "0,1,2,3",
704 "CounterHTOff": "0,1,2,3,4,5,6,7"
707 "EventCode": "0xA1",
708 "UMask": "0x20",
710 "Counter": "0,1,2,3",
713 "CounterHTOff": "0,1,2,3,4,5,6,7"
716 "EventCode": "0xA1",
717 "UMask": "0x40",
719 "Counter": "0,1,2,3",
723 "CounterHTOff": "0,1,2,3,4,5,6,7"
726 "EventCode": "0xA1",
727 "UMask": "0x40",
729 "Counter": "0,1,2,3",
734 "CounterHTOff": "0,1,2,3,4,5,6,7"
737 "EventCode": "0xA1",
738 "UMask": "0x40",
740 "Counter": "0,1,2,3",
743 "CounterHTOff": "0,1,2,3,4,5,6,7"
746 "EventCode": "0xA1",
747 "UMask": "0x80",
749 "Counter": "0,1,2,3",
753 "CounterHTOff": "0,1,2,3,4,5,6,7"
756 "EventCode": "0xA1",
757 "UMask": "0x80",
759 "Counter": "0,1,2,3",
763 "CounterHTOff": "0,1,2,3,4,5,6,7"
766 "EventCode": "0xA1",
767 "UMask": "0x80",
769 "Counter": "0,1,2,3",
772 "CounterHTOff": "0,1,2,3,4,5,6,7"
775 "EventCode": "0xA2",
776 "UMask": "0x1",
777 "BriefDescription": "Resource-related stall cycles",
778 "Counter": "0,1,2,3",
783 "CounterHTOff": "0,1,2,3,4,5,6,7"
786 "EventCode": "0xA2",
787 "UMask": "0x4",
789 "Counter": "0,1,2,3",
792 "CounterHTOff": "0,1,2,3,4,5,6,7"
795 "EventCode": "0xA2",
796 "UMask": "0x8",
798 "Counter": "0,1,2,3",
802 "CounterHTOff": "0,1,2,3,4,5,6,7"
805 "EventCode": "0xA2",
806 "UMask": "0x10",
807 "BriefDescription": "Cycles stalled due to re-order buffer full.",
808 "Counter": "0,1,2,3",
811 "CounterHTOff": "0,1,2,3,4,5,6,7"
814 "EventCode": "0xA3",
815 "UMask": "0x1",
817 "Counter": "0,1,2,3",
823 "CounterHTOff": "0,1,2,3,4,5,6,7"
826 "EventCode": "0xA3",
827 "UMask": "0x2",
829 "Counter": "0,1,2,3",
834 "CounterHTOff": "0,1,2,3"
837 "EventCode": "0xA3",
838 "UMask": "0x4",
840 "Counter": "0,1,2,3",
845 "CounterHTOff": "0,1,2,3"
848 "EventCode": "0xA3",
849 "UMask": "0x5",
851 "Counter": "0,1,2,3",
856 "CounterHTOff": "0,1,2,3"
859 "EventCode": "0xA3",
860 "UMask": "0x6",
862 "Counter": "0,1,2,3",
867 "CounterHTOff": "0,1,2,3"
870 "EventCode": "0xA3",
871 "UMask": "0x8",
881 "EventCode": "0xA3",
882 "UMask": "0xc",
887 "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.",
892 "EventCode": "0xa8",
893 "UMask": "0x1",
895 "Counter": "0,1,2,3",
899 "CounterHTOff": "0,1,2,3,4,5,6,7"
902 "EventCode": "0xA8",
903 "UMask": "0x1",
905 "Counter": "0,1,2,3",
909 "CounterHTOff": "0,1,2,3,4,5,6,7"
912 "EventCode": "0xA8",
913 "UMask": "0x1",
915 "Counter": "0,1,2,3",
919 "CounterHTOff": "0,1,2,3,4,5,6,7"
923 "EventCode": "0xB1",
924 "UMask": "0x1",
926 "Counter": "0,1,2,3",
931 "CounterHTOff": "0,1,2,3"
934 "EventCode": "0xB1",
935 "UMask": "0x1",
936 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
937 "Counter": "0,1,2,3",
943 "CounterHTOff": "0,1,2,3"
946 "EventCode": "0xB1",
947 "UMask": "0x1",
948 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
949 "Counter": "0,1,2,3",
955 "CounterHTOff": "0,1,2,3"
958 "EventCode": "0xB1",
959 "UMask": "0x1",
960 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
961 "Counter": "0,1,2,3",
963 "CounterMask": "3",
967 "CounterHTOff": "0,1,2,3"
970 "EventCode": "0xB1",
971 "UMask": "0x1",
972 "BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
973 "Counter": "0,1,2,3",
978 "CounterHTOff": "0,1,2,3"
981 "EventCode": "0xB1",
982 "UMask": "0x2",
984 "Counter": "0,1,2,3",
987 "PublicDescription": "Counts total number of uops to be executed per-core each cycle.",
989 "CounterHTOff": "0,1,2,3,4,5,6,7"
992 "EventCode": "0xb1",
993 "UMask": "0x2",
994 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
995 "Counter": "0,1,2,3",
1000 "CounterHTOff": "0,1,2,3,4,5,6,7"
1003 "EventCode": "0xb1",
1004 "UMask": "0x2",
1005 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1006 "Counter": "0,1,2,3",
1011 "CounterHTOff": "0,1,2,3,4,5,6,7"
1014 "EventCode": "0xb1",
1015 "UMask": "0x2",
1016 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1017 "Counter": "0,1,2,3",
1019 "CounterMask": "3",
1022 "CounterHTOff": "0,1,2,3,4,5,6,7"
1025 "EventCode": "0xb1",
1026 "UMask": "0x2",
1027 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1028 "Counter": "0,1,2,3",
1033 "CounterHTOff": "0,1,2,3,4,5,6,7"
1037 "EventCode": "0xb1",
1038 "UMask": "0x2",
1039 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1040 "Counter": "0,1,2,3",
1044 "CounterHTOff": "0,1,2,3,4,5,6,7"
1047 "EventCode": "0xC0",
1048 "UMask": "0x0",
1049 … "BriefDescription": "Number of instructions retired. General Counter - architectural event",
1050 "Counter": "0,1,2,3",
1055 "CounterHTOff": "0,1,2,3,4,5,6,7"
1058 "EventCode": "0xC0",
1059 "UMask": "0x1",
1070 "EventCode": "0xC0",
1071 "UMask": "0x2",
1073 "Counter": "0,1,2,3",
1075 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
1077 "CounterHTOff": "0,1,2,3,4,5,6,7"
1080 "EventCode": "0xC1",
1081 "UMask": "0x40",
1083 "Counter": "0,1,2,3",
1087 "CounterHTOff": "0,1,2,3,4,5,6,7"
1090 "EventCode": "0xC2",
1091 "UMask": "0x1",
1095 "Counter": "0,1,2,3",
1097 …"PublicDescription": "Counts the number of micro-ops retired. Use Cmask=1 and invert to count acti…
1099 "CounterHTOff": "0,1,2,3,4,5,6,7"
1103 "EventCode": "0xC2",
1104 "UMask": "0x1",
1106 "Counter": "0,1,2,3",
1110 "CounterHTOff": "0,1,2,3"
1114 "EventCode": "0xC2",
1115 "UMask": "0x1",
1117 "Counter": "0,1,2,3",
1121 "CounterHTOff": "0,1,2,3"
1125 "EventCode": "0xC2",
1126 "UMask": "0x1",
1128 "Counter": "0,1,2,3",
1133 "CounterHTOff": "0,1,2,3"
1136 "EventCode": "0xC2",
1137 "UMask": "0x2",
1140 "Counter": "0,1,2,3",
1142 …used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4…
1144 "CounterHTOff": "0,1,2,3,4,5,6,7"
1147 "EventCode": "0xC3",
1148 "UMask": "0x1",
1149 …"BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nuke…
1150 "Counter": "0,1,2,3",
1153 "CounterHTOff": "0,1,2,3,4,5,6,7"
1157 "EventCode": "0xC3",
1158 "UMask": "0x1",
1160 "Counter": "0,1,2,3",
1164 "CounterHTOff": "0,1,2,3,4,5,6,7"
1167 "EventCode": "0xC3",
1168 "UMask": "0x4",
1169 "BriefDescription": "Self-modifying code (SMC) detected.",
1170 "Counter": "0,1,2,3",
1172 …"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which …
1174 "CounterHTOff": "0,1,2,3,4,5,6,7"
1177 "EventCode": "0xC3",
1178 "UMask": "0x20",
1179 …el AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
1180 "Counter": "0,1,2,3",
1183 "CounterHTOff": "0,1,2,3,4,5,6,7"
1186 "EventCode": "0xC4",
1187 "UMask": "0x0",
1189 "Counter": "0,1,2,3",
1193 "CounterHTOff": "0,1,2,3,4,5,6,7"
1196 "EventCode": "0xC4",
1197 "UMask": "0x1",
1200 "Counter": "0,1,2,3",
1204 "CounterHTOff": "0,1,2,3,4,5,6,7"
1207 "EventCode": "0xC4",
1208 "UMask": "0x2",
1211 "Counter": "0,1,2,3",
1214 "CounterHTOff": "0,1,2,3,4,5,6,7"
1217 "EventCode": "0xC4",
1218 "UMask": "0x2",
1219 …riefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
1221 "Counter": "0,1,2,3",
1224 "CounterHTOff": "0,1,2,3,4,5,6,7"
1227 "EventCode": "0xC4",
1228 "UMask": "0x4",
1231 "Counter": "0,1,2,3",
1234 "CounterHTOff": "0,1,2,3"
1237 "EventCode": "0xC4",
1238 "UMask": "0x8",
1241 "Counter": "0,1,2,3",
1245 "CounterHTOff": "0,1,2,3,4,5,6,7"
1248 "EventCode": "0xC4",
1249 "UMask": "0x10",
1251 "Counter": "0,1,2,3",
1255 "CounterHTOff": "0,1,2,3,4,5,6,7"
1258 "EventCode": "0xC4",
1259 "UMask": "0x20",
1262 "Counter": "0,1,2,3",
1266 "CounterHTOff": "0,1,2,3,4,5,6,7"
1269 "EventCode": "0xC4",
1270 "UMask": "0x40",
1272 "Counter": "0,1,2,3",
1276 "CounterHTOff": "0,1,2,3,4,5,6,7"
1279 "EventCode": "0xC5",
1280 "UMask": "0x0",
1282 "Counter": "0,1,2,3",
1286 "CounterHTOff": "0,1,2,3,4,5,6,7"
1289 "EventCode": "0xC5",
1290 "UMask": "0x1",
1293 "Counter": "0,1,2,3",
1296 "CounterHTOff": "0,1,2,3,4,5,6,7"
1299 "EventCode": "0xC5",
1300 "UMask": "0x4",
1303 "Counter": "0,1,2,3",
1307 "CounterHTOff": "0,1,2,3"
1310 "EventCode": "0xC5",
1311 "UMask": "0x20",
1314 "Counter": "0,1,2,3",
1318 "CounterHTOff": "0,1,2,3,4,5,6,7"
1321 "EventCode": "0xCC",
1322 "UMask": "0x20",
1324 "Counter": "0,1,2,3",
1328 "CounterHTOff": "0,1,2,3,4,5,6,7"
1331 "EventCode": "0xe6",
1332 "UMask": "0x1f",
1334 "Counter": "0,1,2,3",
1336 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
1338 "CounterHTOff": "0,1,2,3,4,5,6,7"