Lines Matching +full:per +full:- +full:cpu

7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
10 …nd undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
14 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
18 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4…
21 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
24 …ue to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.",
25 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY…
28 …-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work…
32 …"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETI…
35 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
38 …ting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
39 …- ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTE…
42 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
49 …ate the maximum 4 uops retired per cycle has been achieved.  Maximizing Retiring typically increas…
52 … that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.",
56 …per cycle has been achieved.  Maximizing Retiring typically increases the Instruction-Per-Cycle me…
59         "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
65         "BriefDescription": "Uops Per Instruction",
71         "BriefDescription": "Instruction per taken branch",
77         "BriefDescription": "Branch instructions per taken branch. ",
95         "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
101 …   "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
107         "BriefDescription": "Total issue-pipeline slots (per-Physical Core)",
113         "BriefDescription": "Total issue-pipeline slots (per-Physical Core)",
119         "BriefDescription": "Instructions per Load (lower number means higher occurance rate)",
125         "BriefDescription": "Instructions per Store (lower number means higher occurance rate)",
131         "BriefDescription": "Instructions per Branch (lower number means higher occurance rate)",
137 …      "BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)",
149         "BriefDescription": "Instructions Per Cycle (per physical core)",
155         "BriefDescription": "Instructions Per Cycle (per physical core)",
161 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
162 …cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) ) i…
167 …   "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
179 … "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)",
185 …BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
215         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
221         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
227         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
233 …"BriefDescription": "L2 cache misses per kilo instruction for all request types (including specula…
239 …"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculati…
245         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
251         "BriefDescription": "Average CPU Utilization",
264 …"MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_…
299         "BriefDescription": "C3 residency percent per core",
300         "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
305         "BriefDescription": "C6 residency percent per core",
306         "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
311         "BriefDescription": "C7 residency percent per core",
312         "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
317         "BriefDescription": "C2 residency percent per package",
318         "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
323         "BriefDescription": "C3 residency percent per package",
324         "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
329         "BriefDescription": "C6 residency percent per package",
330         "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
335         "BriefDescription": "C7 residency percent per package",
336         "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",