Lines Matching +full:7 +full:k

10         "CounterHTOff": "0,1,2,3,4,5,6,7"
13 …"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in …
19 …oad Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
20         "CounterHTOff": "0,1,2,3,4,5,6,7"
30         "CounterHTOff": "0,1,2,3,4,5,6,7"
39         "CounterHTOff": "0,1,2,3,4,5,6,7"
49         "CounterHTOff": "0,1,2,3,4,5,6,7"
59         "CounterHTOff": "0,1,2,3,4,5,6,7"
62 …"PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB le…
68         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K)",
69         "CounterHTOff": "0,1,2,3,4,5,6,7"
79         "CounterHTOff": "0,1,2,3,4,5,6,7"
89         "CounterHTOff": "0,1,2,3,4,5,6,7"
99         "CounterHTOff": "0,1,2,3,4,5,6,7"
102 …  "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
109         "CounterHTOff": "0,1,2,3,4,5,6,7"
112 …ption": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.",
118         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
119         "CounterHTOff": "0,1,2,3,4,5,6,7"
129         "CounterHTOff": "0,1,2,3,4,5,6,7"
138         "CounterHTOff": "0,1,2,3,4,5,6,7"
141 …ption": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
148         "CounterHTOff": "0,1,2,3,4,5,6,7"
158         "CounterHTOff": "0,1,2,3,4,5,6,7"
161 …"PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB l…
167         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K)",
168         "CounterHTOff": "0,1,2,3,4,5,6,7"
178         "CounterHTOff": "0,1,2,3,4,5,6,7"
188         "CounterHTOff": "0,1,2,3,4,5,6,7"
198         "CounterHTOff": "0,1,2,3,4,5,6,7"
207         "CounterHTOff": "0,1,2,3,4,5,6,7"
217         "CounterHTOff": "0,1,2,3,4,5,6,7"
220         "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.",
226         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
227         "CounterHTOff": "0,1,2,3,4,5,6,7"
237         "CounterHTOff": "0,1,2,3,4,5,6,7"
246         "CounterHTOff": "0,1,2,3,4,5,6,7"
256         "CounterHTOff": "0,1,2,3,4,5,6,7"
266         "CounterHTOff": "0,1,2,3,4,5,6,7"
269         "PublicDescription": "ITLB misses that hit STLB (4K).",
275         "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K)",
276         "CounterHTOff": "0,1,2,3,4,5,6,7"
286         "CounterHTOff": "0,1,2,3,4,5,6,7"
296         "CounterHTOff": "0,1,2,3,4,5,6,7"
299         "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
305 …      "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
306         "CounterHTOff": "0,1,2,3,4,5,6,7"
472         "CounterHTOff": "0,1,2,3,4,5,6,7"
482         "CounterHTOff": "0,1,2,3,4,5,6,7"