Lines Matching +full:1 +full:- +full:5
3 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
14 "Counter": "Fixed counter 1",
19 "CounterHTOff": "Fixed counter 1"
22 "Counter": "Fixed counter 1",
24 "AnyThread": "1",
28 "CounterHTOff": "Fixed counter 1"
42 "Counter": "0,1,2,3",
47 "CounterHTOff": "0,1,2,3,4,5,6,7"
52 "Counter": "0,1,2,3",
57 "CounterHTOff": "0,1,2,3,4,5,6,7"
62 "Counter": "0,1,2,3",
67 "CounterHTOff": "0,1,2,3,4,5,6,7"
72 "Counter": "0,1,2,3",
77 "CounterMask": "1",
78 "CounterHTOff": "0,1,2,3,4,5,6,7"
83 "Counter": "0,1,2,3",
85 "AnyThread": "1",
89 "CounterMask": "1",
90 "CounterHTOff": "0,1,2,3,4,5,6,7"
93 …ued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stag…
95 "Counter": "0,1,2,3",
100 "CounterHTOff": "0,1,2,3,4,5,6,7"
104 "Invert": "1",
105 "Counter": "0,1,2,3",
110 "CounterMask": "1",
111 "CounterHTOff": "0,1,2,3"
115 "Invert": "1",
116 "Counter": "0,1,2,3",
118 "AnyThread": "1",
122 "CounterMask": "1",
123 "CounterHTOff": "0,1,2,3"
126 "PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.",
128 "Counter": "0,1,2,3",
132 …"BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensiti…
133 "CounterHTOff": "0,1,2,3,4,5,6,7"
138 "Counter": "0,1,2,3",
143 "CounterHTOff": "0,1,2,3,4,5,6,7"
148 "Counter": "0,1,2,3",
153 "CounterHTOff": "0,1,2,3,4,5,6,7"
157 "Counter": "0,1,2,3",
162 "CounterHTOff": "0,1,2,3,4,5,6,7"
167 "Counter": "0,1,2,3",
172 "CounterHTOff": "0,1,2,3,4,5,6,7"
176 "Counter": "0,1,2,3",
178 "AnyThread": "1",
182 "CounterHTOff": "0,1,2,3,4,5,6,7"
187 "Counter": "0,1,2,3",
192 "CounterHTOff": "0,1,2,3,4,5,6,7"
197 "Counter": "0,1,2,3",
199 "AnyThread": "1",
203 "CounterHTOff": "0,1,2,3,4,5,6,7"
208 "Counter": "0,1,2,3",
213 "CounterHTOff": "0,1,2,3,4,5,6,7"
218 "Counter": "0,1,2,3",
220 "AnyThread": "1",
224 "CounterHTOff": "0,1,2,3,4,5,6,7"
228 "Counter": "0,1,2,3",
233 "CounterHTOff": "0,1,2,3"
237 "Counter": "0,1,2,3",
242 "CounterHTOff": "0,1,2,3,4,5,6,7"
245 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefe…
247 "Counter": "0,1,2,3",
251 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
252 "CounterHTOff": "0,1,2,3,4,5,6,7"
255 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefe…
257 "Counter": "0,1,2,3",
261 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
262 "CounterHTOff": "0,1,2,3,4,5,6,7"
267 "Counter": "0,1,2,3",
272 "CounterHTOff": "0,1,2,3,4,5,6,7"
277 "Counter": "0,1,2,3",
282 "CounterHTOff": "0,1,2,3,4,5,6,7"
287 "Counter": "0,1,2,3",
292 "CounterHTOff": "0,1,2,3,4,5,6,7"
297 "Counter": "0,1,2,3",
302 "CounterHTOff": "0,1,2,3,4,5,6,7"
305 …micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an u…
307 "Counter": "0,1,2,3",
312 "CounterHTOff": "0,1,2,3,4,5,6,7"
316 "Invert": "1",
317 "Counter": "0,1,2,3",
319 "EdgeDetect": "1",
323 "CounterMask": "1",
324 "CounterHTOff": "0,1,2,3,4,5,6,7"
329 "Counter": "0,1,2,3",
334 "CounterHTOff": "0,1,2,3,4,5,6,7"
339 "Counter": "0,1,2,3",
344 "CounterHTOff": "0,1,2,3,4,5,6,7"
348 "Counter": "0,1,2,3",
352 "BriefDescription": "Not taken macro-conditional branches.",
353 "CounterHTOff": "0,1,2,3,4,5,6,7"
357 "Counter": "0,1,2,3",
361 "BriefDescription": "Taken speculative and retired macro-conditional branches.",
362 "CounterHTOff": "0,1,2,3,4,5,6,7"
366 "Counter": "0,1,2,3",
370 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
371 "CounterHTOff": "0,1,2,3,4,5,6,7"
375 "Counter": "0,1,2,3",
380 "CounterHTOff": "0,1,2,3,4,5,6,7"
384 "Counter": "0,1,2,3",
389 "CounterHTOff": "0,1,2,3,4,5,6,7"
393 "Counter": "0,1,2,3",
398 "CounterHTOff": "0,1,2,3,4,5,6,7"
402 "Counter": "0,1,2,3",
407 "CounterHTOff": "0,1,2,3,4,5,6,7"
411 "Counter": "0,1,2,3",
415 "BriefDescription": "Speculative and retired macro-conditional branches.",
416 "CounterHTOff": "0,1,2,3,4,5,6,7"
420 "Counter": "0,1,2,3",
424 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
425 "CounterHTOff": "0,1,2,3,4,5,6,7"
429 "Counter": "0,1,2,3",
434 "CounterHTOff": "0,1,2,3,4,5,6,7"
438 "Counter": "0,1,2,3",
443 "CounterHTOff": "0,1,2,3,4,5,6,7"
447 "Counter": "0,1,2,3",
452 "CounterHTOff": "0,1,2,3,4,5,6,7"
457 "Counter": "0,1,2,3",
462 "CounterHTOff": "0,1,2,3,4,5,6,7"
466 "Counter": "0,1,2,3",
471 "CounterHTOff": "0,1,2,3,4,5,6,7"
475 "Counter": "0,1,2,3",
480 "CounterHTOff": "0,1,2,3,4,5,6,7"
484 "Counter": "0,1,2,3",
489 "CounterHTOff": "0,1,2,3,4,5,6,7"
493 "Counter": "0,1,2,3",
498 "CounterHTOff": "0,1,2,3,4,5,6,7"
502 "Counter": "0,1,2,3",
507 "CounterHTOff": "0,1,2,3,4,5,6,7"
511 "Counter": "0,1,2,3",
516 "CounterHTOff": "0,1,2,3,4,5,6,7"
520 "Counter": "0,1,2,3",
525 "CounterHTOff": "0,1,2,3,4,5,6,7"
530 "Counter": "0,1,2,3",
535 "CounterHTOff": "0,1,2,3,4,5,6,7"
540 "Counter": "0,1,2,3",
545 "CounterHTOff": "0,1,2,3,4,5,6,7"
550 "Counter": "0,1,2,3",
552 "AnyThread": "1",
556 "CounterHTOff": "0,1,2,3,4,5,6,7"
560 "Counter": "0,1,2,3",
565 "CounterHTOff": "0,1,2,3,4,5,6,7"
568 "PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.",
570 "Counter": "0,1,2,3",
574 "BriefDescription": "Cycles per thread when uops are executed in port 1",
575 "CounterHTOff": "0,1,2,3,4,5,6,7"
578 "PublicDescription": "Cycles per core when uops are exectuted in port 1.",
580 "Counter": "0,1,2,3",
582 "AnyThread": "1",
585 "BriefDescription": "Cycles per core when uops are executed in port 1.",
586 "CounterHTOff": "0,1,2,3,4,5,6,7"
590 "Counter": "0,1,2,3",
594 "BriefDescription": "Cycles per thread when uops are executed in port 1.",
595 "CounterHTOff": "0,1,2,3,4,5,6,7"
600 "Counter": "0,1,2,3",
605 "CounterHTOff": "0,1,2,3,4,5,6,7"
609 "Counter": "0,1,2,3",
611 "AnyThread": "1",
615 "CounterHTOff": "0,1,2,3,4,5,6,7"
619 "Counter": "0,1,2,3",
624 "CounterHTOff": "0,1,2,3,4,5,6,7"
629 "Counter": "0,1,2,3",
634 "CounterHTOff": "0,1,2,3,4,5,6,7"
638 "Counter": "0,1,2,3",
640 "AnyThread": "1",
644 "CounterHTOff": "0,1,2,3,4,5,6,7"
648 "Counter": "0,1,2,3",
653 "CounterHTOff": "0,1,2,3,4,5,6,7"
658 "Counter": "0,1,2,3",
663 "CounterHTOff": "0,1,2,3,4,5,6,7"
668 "Counter": "0,1,2,3",
670 "AnyThread": "1",
674 "CounterHTOff": "0,1,2,3,4,5,6,7"
678 "Counter": "0,1,2,3",
683 "CounterHTOff": "0,1,2,3,4,5,6,7"
686 "PublicDescription": "Cycles which a uop is dispatched on port 5 in this thread.",
688 "Counter": "0,1,2,3",
692 "BriefDescription": "Cycles per thread when uops are executed in port 5",
693 "CounterHTOff": "0,1,2,3,4,5,6,7"
696 "PublicDescription": "Cycles per core when uops are exectuted in port 5.",
698 "Counter": "0,1,2,3",
700 "AnyThread": "1",
703 "BriefDescription": "Cycles per core when uops are executed in port 5.",
704 "CounterHTOff": "0,1,2,3,4,5,6,7"
708 "Counter": "0,1,2,3",
712 "BriefDescription": "Cycles per thread when uops are executed in port 5.",
713 "CounterHTOff": "0,1,2,3,4,5,6,7"
718 "Counter": "0,1,2,3",
723 "CounterHTOff": "0,1,2,3,4,5,6,7"
728 "Counter": "0,1,2,3",
730 "AnyThread": "1",
734 "CounterHTOff": "0,1,2,3,4,5,6,7"
738 "Counter": "0,1,2,3",
743 "CounterHTOff": "0,1,2,3,4,5,6,7"
748 "Counter": "0,1,2,3",
753 "CounterHTOff": "0,1,2,3,4,5,6,7"
757 "Counter": "0,1,2,3",
759 "AnyThread": "1",
763 "CounterHTOff": "0,1,2,3,4,5,6,7"
767 "Counter": "0,1,2,3",
772 "CounterHTOff": "0,1,2,3,4,5,6,7"
777 "Counter": "0,1,2,3",
782 "BriefDescription": "Resource-related stall cycles",
783 "CounterHTOff": "0,1,2,3,4,5,6,7"
787 "Counter": "0,1,2,3",
792 "CounterHTOff": "0,1,2,3,4,5,6,7"
797 "Counter": "0,1,2,3",
802 "CounterHTOff": "0,1,2,3,4,5,6,7"
806 "Counter": "0,1,2,3",
810 "BriefDescription": "Cycles stalled due to re-order buffer full.",
811 "CounterHTOff": "0,1,2,3,4,5,6,7"
816 "Counter": "0,1,2,3",
822 "CounterMask": "1",
823 "CounterHTOff": "0,1,2,3,4,5,6,7"
828 "Counter": "0,1,2,3",
834 "CounterHTOff": "0,1,2,3"
839 "Counter": "0,1,2,3",
843 …"BriefDescription": "This event increments by 1 for every cycle where there was no execute for thi…
845 "CounterHTOff": "0,1,2,3"
850 "Counter": "0,1,2,3",
855 "CounterMask": "5",
856 "CounterHTOff": "0,1,2,3"
861 "Counter": "0,1,2,3",
867 "CounterHTOff": "0,1,2,3"
894 "Counter": "0,1,2,3",
899 "CounterHTOff": "0,1,2,3,4,5,6,7"
903 "Counter": "0,1,2,3",
908 "CounterMask": "1",
909 "CounterHTOff": "0,1,2,3,4,5,6,7"
913 "Counter": "0,1,2,3",
919 "CounterHTOff": "0,1,2,3,4,5,6,7"
923 "Invert": "1",
924 "Counter": "0,1,2,3",
930 "CounterMask": "1",
931 "CounterHTOff": "0,1,2,3"
936 "Counter": "0,1,2,3",
941 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
942 "CounterMask": "1",
943 "CounterHTOff": "0,1,2,3"
948 "Counter": "0,1,2,3",
953 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
955 "CounterHTOff": "0,1,2,3"
960 "Counter": "0,1,2,3",
965 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
967 "CounterHTOff": "0,1,2,3"
971 "Counter": "0,1,2,3",
976 "BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
978 "CounterHTOff": "0,1,2,3"
981 "PublicDescription": "Counts total number of uops to be executed per-core each cycle.",
983 "Counter": "0,1,2,3",
989 "CounterHTOff": "0,1,2,3,4,5,6,7"
993 "Counter": "0,1,2,3",
998 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
999 "CounterMask": "1",
1000 "CounterHTOff": "0,1,2,3,4,5,6,7"
1004 "Counter": "0,1,2,3",
1009 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1011 "CounterHTOff": "0,1,2,3,4,5,6,7"
1015 "Counter": "0,1,2,3",
1020 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1022 "CounterHTOff": "0,1,2,3,4,5,6,7"
1026 "Counter": "0,1,2,3",
1031 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1033 "CounterHTOff": "0,1,2,3,4,5,6,7"
1037 "Invert": "1",
1038 "Counter": "0,1,2,3",
1043 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1044 "CounterHTOff": "0,1,2,3,4,5,6,7"
1049 "Counter": "0,1,2,3",
1054 … "BriefDescription": "Number of instructions retired. General Counter - architectural event",
1055 "CounterHTOff": "0,1,2,3,4,5,6,7"
1061 "Counter": "1",
1067 "CounterHTOff": "1"
1070 "PEBS": "1",
1073 "Counter": "0,1,2,3",
1078 "CounterHTOff": "0,1,2,3,4,5,6,7"
1081 "PEBS": "1",
1084 "Counter": "0,1,2,3",
1088 "CounterHTOff": "0,1,2,3,4,5,6,7"
1091 "PEBS": "1",
1093 "Counter": "0,1,2,3",
1098 "CounterHTOff": "0,1,2,3,4,5,6,7",
1099 "Data_LA": "1"
1102 "PEBS": "1",
1105 "Invert": "1",
1106 "Counter": "0,1,2,3",
1111 "CounterMask": "1",
1112 "CounterHTOff": "0,1,2,3"
1115 "PEBS": "1",
1118 "Invert": "1",
1119 "Counter": "0,1,2,3",
1125 "CounterHTOff": "0,1,2,3"
1128 "PEBS": "1",
1131 "Invert": "1",
1132 "Counter": "0,1,2,3",
1134 "AnyThread": "1",
1138 "CounterMask": "1",
1139 "CounterHTOff": "0,1,2,3"
1142 "PEBS": "1",
1144 "Counter": "0,1,2,3",
1149 "CounterHTOff": "0,1,2,3,4,5,6,7"
1153 "Counter": "0,1,2,3",
1157 …"BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nuke…
1158 "CounterHTOff": "0,1,2,3,4,5,6,7"
1162 "Counter": "0,1,2,3",
1164 "EdgeDetect": "1",
1168 "CounterMask": "1",
1169 "CounterHTOff": "0,1,2,3,4,5,6,7"
1172 …"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which …
1174 "Counter": "0,1,2,3",
1178 "BriefDescription": "Self-modifying code (SMC) detected.",
1179 "CounterHTOff": "0,1,2,3,4,5,6,7"
1183 "Counter": "0,1,2,3",
1188 "CounterHTOff": "0,1,2,3,4,5,6,7"
1193 "Counter": "0,1,2,3",
1198 "CounterHTOff": "0,1,2,3,4,5,6,7"
1201 "PEBS": "1",
1203 "Counter": "0,1,2,3",
1208 "CounterHTOff": "0,1,2,3,4,5,6,7"
1211 "PEBS": "1",
1213 "Counter": "0,1,2,3",
1218 "CounterHTOff": "0,1,2,3,4,5,6,7"
1221 "PEBS": "1",
1223 "Counter": "0,1,2,3",
1228 "CounterHTOff": "0,1,2,3,4,5,6,7"
1233 "Counter": "0,1,2,3",
1238 "CounterHTOff": "0,1,2,3"
1241 "PEBS": "1",
1243 "Counter": "0,1,2,3",
1248 "CounterHTOff": "0,1,2,3,4,5,6,7"
1251 "PEBS": "1",
1254 "Counter": "0,1,2,3",
1259 "CounterHTOff": "0,1,2,3,4,5,6,7"
1262 "PEBS": "1",
1264 "Counter": "0,1,2,3",
1269 "CounterHTOff": "0,1,2,3,4,5,6,7"
1272 "PEBS": "1",
1275 "Counter": "0,1,2,3",
1280 "CounterHTOff": "0,1,2,3,4,5,6,7"
1285 "Counter": "0,1,2,3",
1290 "CounterHTOff": "0,1,2,3,4,5,6,7"
1293 "PEBS": "1",
1295 "Counter": "0,1,2,3",
1300 "CounterHTOff": "0,1,2,3,4,5,6,7"
1306 "Counter": "0,1,2,3",
1311 "CounterHTOff": "0,1,2,3"
1314 "PEBS": "1",
1316 "Counter": "0,1,2,3",
1321 "CounterHTOff": "0,1,2,3,4,5,6,7"
1326 "Counter": "0,1,2,3",
1331 "CounterHTOff": "0,1,2,3,4,5,6,7"
1334 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
1336 "Counter": "0,1,2,3",
1341 "CounterHTOff": "0,1,2,3,4,5,6,7"