Lines Matching full:responses

269 …ts demand cacheable data reads of full cache lines have any transaction responses from the uncore …
279 …ts demand cacheable data reads of full cache lines have any transaction responses from the uncore …
344 …uests generated by a write to full data cache line have any transaction responses from the uncore …
354 …uests generated by a write to full data cache line have any transaction responses from the uncore …
419 … prefetch requests that miss the instruction cache have any transaction responses from the uncore …
429 … prefetch requests that miss the instruction cache have any transaction responses from the uncore …
494 …ck transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore …
504 …ck transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore …
569 …ne reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore …
579 …ne reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore …
644 …wnership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore …
654 …wnership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore …
719 …ription": "Counts bus lock and split lock requests have any transaction responses from the uncore …
729 …"BriefDescription": "Counts bus lock and split lock requests have any transaction responses from t…
794 …ory region and full cache-line non-temporal writes have any transaction responses from the uncore …
804 …ory region and full cache-line non-temporal writes have any transaction responses from the uncore …
869 …e lines requests by software prefetch instructions have any transaction responses from the uncore …
879 …e lines requests by software prefetch instructions have any transaction responses from the uncore …
944 …ads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore …
954 …ads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore …
1019 … uncacheable write combining (USWC) memory region  have any transaction responses from the uncore …
1029 … uncacheable write combining (USWC) memory region  have any transaction responses from the uncore …
1094 …ription": "Counts requests to the uncore subsystem have any transaction responses from the uncore …
1104 …"BriefDescription": "Counts requests to the uncore subsystem have any transaction responses from t…
1169 …ounts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore …
1179 …ounts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore …
1244 …"PublicDescription": "Counts data reads (demand & prefetch) have any transaction responses from th…
1254 …"BriefDescription": "Counts data reads (demand & prefetch) have any transaction responses from the…
1319 …s for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore …
1329 …s for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore …
1394 …d for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore …
1404 …d for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore …