Lines Matching +full:front +full:- +full:end

9 …"PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resour…
37 …er an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was …
50 …er an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was …
63 …ter an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was …
71 …delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles.…
111         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
117         "PublicDescription": "Cycles with less than 3 uops delivered by the front-end.",
133 …Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) mi…
141 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
184 …) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation T…
189         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
194 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
199 …d after an interval where the front-end delivered no uops for a period of 8 cycles which was not i…
207 …ions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this …
213 …d after an interval where the front-end delivered no uops for a period of 2 cycles which was not i…
226 …d after an interval where the front-end delivered no uops for a period of 4 cycles which was not i…
250         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
255 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
260         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
268 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n…
274 …tch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
283 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not …
302 …"PublicDescription": "Counts, on the per-thread basis, cycles when less than 1 uop is delivered to…
307 …etch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
316 …d after an interval where the front-end delivered no uops for a period of 64 cycles which was not …
353 … after an interval where the front-end delivered no uops for a period of 256 cycles which was not …
387 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc…
392 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
397 …d after an interval where the front-end delivered no uops for a period of 16 cycles which was not …
405 …ons that are delivered to the back-end after a front-end stall of at least 16 cycles. During this …
411         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
417         "PublicDescription": "Cycles with less than 2 uops delivered by the front-end.",
422 …d after an interval where the front-end delivered no uops for a period of 32 cycles which was not …
430 …ons that are delivered to the back-end after a front-end stall of at least 32 cycles. During this …
473 … after an interval where the front-end delivered no uops for a period of 512 cycles which was not …