Lines Matching full:decode

27 …"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while …
32 …Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while …
88 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (M…
122 …ption": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream…
128 …ycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stre…
133 …"BriefDescription": "Retired Instructions who experienced decode stream buffer (DSB - the decoded …
141 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
147         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
152 …Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also…
157 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while …
163 …tion Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that ma…
168 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M…
174 …on": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from t…
184 …Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3…
189         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
194 …Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops ro…
239 …cription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instru…
245 …nts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instru…
250         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
255 …event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses be…
343 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe…
348 …tion": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stre…
371 …de line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at …
382 …Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'b…
436 …"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pip…
443 …"PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pi…
462         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
468 …ts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre…
492 …Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'b…
497         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
503 … the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stre…