Lines Matching +full:0 +full:- +full:3
3 "UMask": "0x1",
5 "Counter": "Fixed counter 0",
7 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
9 "CounterHTOff": "Fixed counter 0"
12 "UMask": "0x2",
21 "UMask": "0x2",
30 "UMask": "0x3",
39 "EventCode": "0x03",
40 "UMask": "0x2",
41 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
42 "Counter": "0,1,2,3",
44 …-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store…
46 "CounterHTOff": "0,1,2,3,4,5,6,7"
49 "EventCode": "0x03",
50 "UMask": "0x8",
52 "Counter": "0,1,2,3",
55 "CounterHTOff": "0,1,2,3,4,5,6,7"
58 "EventCode": "0x07",
59 "UMask": "0x1",
61 "Counter": "0,1,2,3",
65 "CounterHTOff": "0,1,2,3,4,5,6,7"
68 "EventCode": "0x0D",
69 "UMask": "0x3",
71 "Counter": "0,1,2,3",
76 "CounterHTOff": "0,1,2,3,4,5,6,7"
79 "EventCode": "0x0D",
80 "UMask": "0x3",
82 "Counter": "0,1,2,3",
87 "CounterHTOff": "0,1,2,3,4,5,6,7"
90 "EventCode": "0x0D",
91 "UMask": "0x8",
93 "Counter": "0,1,2,3",
97 "CounterHTOff": "0,1,2,3,4,5,6,7"
100 "EventCode": "0x0E",
101 "UMask": "0x1",
103 "Counter": "0,1,2,3",
107 "CounterHTOff": "0,1,2,3,4,5,6,7"
111 "EventCode": "0x0E",
112 "UMask": "0x1",
114 "Counter": "0,1,2,3",
119 "CounterHTOff": "0,1,2,3"
122 "EventCode": "0x0E",
123 "UMask": "0x10",
124 …"BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensiti…
125 "Counter": "0,1,2,3",
127 …ublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitiv…
129 "CounterHTOff": "0,1,2,3,4,5,6,7"
132 "EventCode": "0x0E",
133 "UMask": "0x20",
134 …w LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sour…
135 "Counter": "0,1,2,3",
138 "CounterHTOff": "0,1,2,3,4,5,6,7"
141 "EventCode": "0x0E",
142 "UMask": "0x40",
144 "Counter": "0,1,2,3",
147 "CounterHTOff": "0,1,2,3,4,5,6,7"
150 "EventCode": "0x14",
151 "UMask": "0x1",
153 "Counter": "0,1,2,3",
155 …: "This event counts the number of the divide operations executed. Uses edge-detect and a cmask va…
157 "CounterHTOff": "0,1,2,3,4,5,6,7"
160 "EventCode": "0x3C",
161 "UMask": "0x0",
163 "Counter": "0,1,2,3",
167 "CounterHTOff": "0,1,2,3,4,5,6,7"
170 "EventCode": "0x3C",
171 "UMask": "0x0",
173 "Counter": "0,1,2,3",
177 "CounterHTOff": "0,1,2,3,4,5,6,7"
180 "EventCode": "0x3C",
181 "UMask": "0x1",
183 "Counter": "0,1,2,3",
185 …"PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts wh…
187 "CounterHTOff": "0,1,2,3,4,5,6,7"
190 "EventCode": "0x3C",
191 "UMask": "0x1",
193 "Counter": "0,1,2,3",
197 "CounterHTOff": "0,1,2,3,4,5,6,7"
200 "EventCode": "0x3C",
201 "UMask": "0x1",
203 "Counter": "0,1,2,3",
207 "CounterHTOff": "0,1,2,3,4,5,6,7"
210 "EventCode": "0x3C",
211 "UMask": "0x1",
213 "Counter": "0,1,2,3",
217 "CounterHTOff": "0,1,2,3,4,5,6,7"
220 "EventCode": "0x3c",
221 "UMask": "0x2",
223 "Counter": "0,1,2,3",
226 "CounterHTOff": "0,1,2,3"
229 "EventCode": "0x3C",
230 "UMask": "0x2",
232 "Counter": "0,1,2,3",
235 "CounterHTOff": "0,1,2,3,4,5,6,7"
238 "EventCode": "0x4c",
239 "UMask": "0x1",
240 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
241 "Counter": "0,1,2,3",
243 …"PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fil…
245 "CounterHTOff": "0,1,2,3,4,5,6,7"
248 "EventCode": "0x4C",
249 "UMask": "0x2",
250 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
251 "Counter": "0,1,2,3",
253 …"PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fil…
255 "CounterHTOff": "0,1,2,3,4,5,6,7"
258 "EventCode": "0x58",
259 "UMask": "0x1",
261 "Counter": "0,1,2,3",
264 "CounterHTOff": "0,1,2,3,4,5,6,7"
267 "EventCode": "0x58",
268 "UMask": "0x2",
270 "Counter": "0,1,2,3",
273 "CounterHTOff": "0,1,2,3,4,5,6,7"
276 "EventCode": "0x58",
277 "UMask": "0x4",
279 "Counter": "0,1,2,3",
282 "CounterHTOff": "0,1,2,3,4,5,6,7"
285 "EventCode": "0x58",
286 "UMask": "0x8",
288 "Counter": "0,1,2,3",
291 "CounterHTOff": "0,1,2,3,4,5,6,7"
294 "EventCode": "0x5E",
295 "UMask": "0x1",
297 "Counter": "0,1,2,3",
299 …vation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. …
301 "CounterHTOff": "0,1,2,3,4,5,6,7"
306 "EventCode": "0x5E",
307 "UMask": "0x1",
309 "Counter": "0,1,2,3",
313 "CounterHTOff": "0,1,2,3,4,5,6,7"
316 "EventCode": "0x87",
317 "UMask": "0x1",
319 "Counter": "0,1,2,3",
321 …he number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penal…
323 "CounterHTOff": "0,1,2,3,4,5,6,7"
326 "EventCode": "0x88",
327 "UMask": "0x41",
328 "BriefDescription": "Not taken macro-conditional branches",
329 "Counter": "0,1,2,3",
331 "PublicDescription": "This event counts not taken macro-conditional branch instructions.",
333 "CounterHTOff": "0,1,2,3,4,5,6,7"
336 "EventCode": "0x88",
337 "UMask": "0x81",
338 "BriefDescription": "Taken speculative and retired macro-conditional branches",
339 "Counter": "0,1,2,3",
341 …"PublicDescription": "This event counts taken speculative and retired macro-conditional branch ins…
343 "CounterHTOff": "0,1,2,3,4,5,6,7"
346 "EventCode": "0x88",
347 "UMask": "0x82",
348 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
349 "Counter": "0,1,2,3",
351 …"PublicDescription": "This event counts taken speculative and retired macro-conditional branch ins…
353 "CounterHTOff": "0,1,2,3,4,5,6,7"
356 "EventCode": "0x88",
357 "UMask": "0x84",
359 "Counter": "0,1,2,3",
363 "CounterHTOff": "0,1,2,3,4,5,6,7"
366 "EventCode": "0x88",
367 "UMask": "0x88",
369 "Counter": "0,1,2,3",
373 "CounterHTOff": "0,1,2,3,4,5,6,7"
376 "EventCode": "0x88",
377 "UMask": "0x90",
379 "Counter": "0,1,2,3",
383 "CounterHTOff": "0,1,2,3,4,5,6,7"
386 "EventCode": "0x88",
387 "UMask": "0xa0",
389 "Counter": "0,1,2,3",
393 "CounterHTOff": "0,1,2,3,4,5,6,7"
396 "EventCode": "0x88",
397 "UMask": "0xc1",
398 "BriefDescription": "Speculative and retired macro-conditional branches",
399 "Counter": "0,1,2,3",
401 …": "This event counts both taken and not taken speculative and retired macro-conditional branch in…
403 "CounterHTOff": "0,1,2,3,4,5,6,7"
406 "EventCode": "0x88",
407 "UMask": "0xc2",
408 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
409 "Counter": "0,1,2,3",
411 …": "This event counts both taken and not taken speculative and retired macro-unconditional branch …
413 "CounterHTOff": "0,1,2,3,4,5,6,7"
416 "EventCode": "0x88",
417 "UMask": "0xc4",
419 "Counter": "0,1,2,3",
423 "CounterHTOff": "0,1,2,3,4,5,6,7"
426 "EventCode": "0x88",
427 "UMask": "0xc8",
429 "Counter": "0,1,2,3",
433 "CounterHTOff": "0,1,2,3,4,5,6,7"
436 "EventCode": "0x88",
437 "UMask": "0xd0",
439 "Counter": "0,1,2,3",
443 "CounterHTOff": "0,1,2,3,4,5,6,7"
446 "EventCode": "0x88",
447 "UMask": "0xff",
449 "Counter": "0,1,2,3",
453 "CounterHTOff": "0,1,2,3,4,5,6,7"
456 "EventCode": "0x89",
457 "UMask": "0x41",
459 "Counter": "0,1,2,3",
463 "CounterHTOff": "0,1,2,3,4,5,6,7"
466 "EventCode": "0x89",
467 "UMask": "0x81",
469 "Counter": "0,1,2,3",
473 "CounterHTOff": "0,1,2,3,4,5,6,7"
476 "EventCode": "0x89",
477 "UMask": "0x84",
479 "Counter": "0,1,2,3",
483 "CounterHTOff": "0,1,2,3,4,5,6,7"
486 "EventCode": "0x89",
487 "UMask": "0x88",
489 "Counter": "0,1,2,3",
493 "CounterHTOff": "0,1,2,3,4,5,6,7"
496 "EventCode": "0x89",
497 "UMask": "0xa0",
499 "Counter": "0,1,2,3",
502 "CounterHTOff": "0,1,2,3,4,5,6,7"
505 "EventCode": "0x89",
506 "UMask": "0xc1",
508 "Counter": "0,1,2,3",
512 "CounterHTOff": "0,1,2,3,4,5,6,7"
515 "EventCode": "0x89",
516 "UMask": "0xc4",
518 "Counter": "0,1,2,3",
522 "CounterHTOff": "0,1,2,3,4,5,6,7"
525 "EventCode": "0x89",
526 "UMask": "0xff",
528 "Counter": "0,1,2,3",
532 "CounterHTOff": "0,1,2,3,4,5,6,7"
535 "EventCode": "0xA0",
536 "UMask": "0x3",
537 …"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file…
538 "Counter": "0,1,2,3",
540 …"PublicDescription": "This event counts the number of micro-operations cancelled after they were d…
542 "CounterHTOff": "0,1,2,3"
545 "EventCode": "0xA1",
546 "UMask": "0x1",
547 "BriefDescription": "Cycles per thread when uops are executed in port 0",
548 "Counter": "0,1,2,3",
550 …is event counts, on the per-thread basis, cycles during which uops are dispatched from the Reserva…
552 "CounterHTOff": "0,1,2,3,4,5,6,7"
555 "EventCode": "0xA1",
556 "UMask": "0x1",
557 "BriefDescription": "Cycles per core when uops are exectuted in port 0.",
558 "Counter": "0,1,2,3",
562 "CounterHTOff": "0,1,2,3,4,5,6,7"
565 "EventCode": "0xA1",
566 "UMask": "0x1",
567 "BriefDescription": "Cycles per thread when uops are executed in port 0",
568 "Counter": "0,1,2,3",
570 …is event counts, on the per-thread basis, cycles during which uops are dispatched from the Reserva…
572 "CounterHTOff": "0,1,2,3,4,5,6,7"
575 "EventCode": "0xA1",
576 "UMask": "0x2",
578 "Counter": "0,1,2,3",
580 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
582 "CounterHTOff": "0,1,2,3,4,5,6,7"
585 "EventCode": "0xA1",
586 "UMask": "0x2",
588 "Counter": "0,1,2,3",
592 "CounterHTOff": "0,1,2,3,4,5,6,7"
595 "EventCode": "0xA1",
596 "UMask": "0x2",
598 "Counter": "0,1,2,3",
600 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
602 "CounterHTOff": "0,1,2,3,4,5,6,7"
605 "EventCode": "0xA1",
606 "UMask": "0x4",
608 "Counter": "0,1,2,3",
610 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
612 "CounterHTOff": "0,1,2,3,4,5,6,7"
615 "EventCode": "0xA1",
616 "UMask": "0x4",
618 "Counter": "0,1,2,3",
622 "CounterHTOff": "0,1,2,3,4,5,6,7"
625 "EventCode": "0xA1",
626 "UMask": "0x4",
628 "Counter": "0,1,2,3",
630 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
632 "CounterHTOff": "0,1,2,3,4,5,6,7"
635 "EventCode": "0xA1",
636 "UMask": "0x8",
637 "BriefDescription": "Cycles per thread when uops are executed in port 3",
638 "Counter": "0,1,2,3",
640 …is event counts, on the per-thread basis, cycles during which uops are dispatched from the Reserva…
642 "CounterHTOff": "0,1,2,3,4,5,6,7"
645 "EventCode": "0xA1",
646 "UMask": "0x8",
647 "BriefDescription": "Cycles per core when uops are dispatched to port 3.",
648 "Counter": "0,1,2,3",
652 "CounterHTOff": "0,1,2,3,4,5,6,7"
655 "EventCode": "0xA1",
656 "UMask": "0x8",
657 "BriefDescription": "Cycles per thread when uops are executed in port 3",
658 "Counter": "0,1,2,3",
660 …is event counts, on the per-thread basis, cycles during which uops are dispatched from the Reserva…
662 "CounterHTOff": "0,1,2,3,4,5,6,7"
665 "EventCode": "0xA1",
666 "UMask": "0x10",
668 "Counter": "0,1,2,3",
670 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
672 "CounterHTOff": "0,1,2,3,4,5,6,7"
675 "EventCode": "0xA1",
676 "UMask": "0x10",
678 "Counter": "0,1,2,3",
682 "CounterHTOff": "0,1,2,3,4,5,6,7"
685 "EventCode": "0xA1",
686 "UMask": "0x10",
688 "Counter": "0,1,2,3",
690 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
692 "CounterHTOff": "0,1,2,3,4,5,6,7"
695 "EventCode": "0xA1",
696 "UMask": "0x20",
698 "Counter": "0,1,2,3",
700 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
702 "CounterHTOff": "0,1,2,3,4,5,6,7"
705 "EventCode": "0xA1",
706 "UMask": "0x20",
708 "Counter": "0,1,2,3",
712 "CounterHTOff": "0,1,2,3,4,5,6,7"
715 "EventCode": "0xA1",
716 "UMask": "0x20",
718 "Counter": "0,1,2,3",
720 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
722 "CounterHTOff": "0,1,2,3,4,5,6,7"
725 "EventCode": "0xA1",
726 "UMask": "0x40",
728 "Counter": "0,1,2,3",
730 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
732 "CounterHTOff": "0,1,2,3,4,5,6,7"
735 "EventCode": "0xA1",
736 "UMask": "0x40",
738 "Counter": "0,1,2,3",
742 "CounterHTOff": "0,1,2,3,4,5,6,7"
745 "EventCode": "0xA1",
746 "UMask": "0x40",
748 "Counter": "0,1,2,3",
750 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
752 "CounterHTOff": "0,1,2,3,4,5,6,7"
755 "EventCode": "0xA1",
756 "UMask": "0x80",
758 "Counter": "0,1,2,3",
760 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
762 "CounterHTOff": "0,1,2,3,4,5,6,7"
765 "EventCode": "0xA1",
766 "UMask": "0x80",
768 "Counter": "0,1,2,3",
772 "CounterHTOff": "0,1,2,3,4,5,6,7"
775 "EventCode": "0xA1",
776 "UMask": "0x80",
778 "Counter": "0,1,2,3",
780 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
782 "CounterHTOff": "0,1,2,3,4,5,6,7"
785 "EventCode": "0xa2",
786 "UMask": "0x1",
787 "BriefDescription": "Resource-related stall cycles",
788 "Counter": "0,1,2,3",
790 "PublicDescription": "This event counts resource-related stall cycles.",
792 "CounterHTOff": "0,1,2,3,4,5,6,7"
795 "EventCode": "0xA2",
796 "UMask": "0x4",
798 "Counter": "0,1,2,3",
802 "CounterHTOff": "0,1,2,3,4,5,6,7"
805 "EventCode": "0xA2",
806 "UMask": "0x8",
808 "Counter": "0,1,2,3",
812 "CounterHTOff": "0,1,2,3,4,5,6,7"
815 "EventCode": "0xA2",
816 "UMask": "0x10",
817 "BriefDescription": "Cycles stalled due to re-order buffer full.",
818 "Counter": "0,1,2,3",
822 "CounterHTOff": "0,1,2,3,4,5,6,7"
825 "EventCode": "0xA3",
826 "UMask": "0x1",
828 "Counter": "0,1,2,3",
833 "CounterHTOff": "0,1,2,3,4,5,6,7"
836 "EventCode": "0xA3",
837 "UMask": "0x1",
839 "Counter": "0,1,2,3",
843 "CounterHTOff": "0,1,2,3,4,5,6,7"
846 "EventCode": "0xA3",
847 "UMask": "0x2",
849 "Counter": "0,1,2,3",
852 …e CPU has at least one pending demand load request (that is cycles with non-completed load waitin…
854 "CounterHTOff": "0,1,2,3,4,5,6,7"
857 "EventCode": "0xA3",
858 "UMask": "0x2",
860 "Counter": "0,1,2,3",
864 "CounterHTOff": "0,1,2,3"
867 "EventCode": "0xA3",
868 "UMask": "0x4",
870 "Counter": "0,1,2,3",
875 "CounterHTOff": "0,1,2,3"
878 "EventCode": "0xA3",
879 "UMask": "0x4",
881 "Counter": "0,1,2,3",
885 "CounterHTOff": "0,1,2,3,4,5,6,7"
888 "EventCode": "0xA3",
889 "UMask": "0x5",
891 "Counter": "0,1,2,3",
896 "CounterHTOff": "0,1,2,3"
899 "EventCode": "0xA3",
900 "UMask": "0x5",
902 "Counter": "0,1,2,3",
906 "CounterHTOff": "0,1,2,3,4,5,6,7"
909 "EventCode": "0xA3",
910 "UMask": "0x6",
912 "Counter": "0,1,2,3",
917 "CounterHTOff": "0,1,2,3"
920 "EventCode": "0xA3",
921 "UMask": "0x6",
923 "Counter": "0,1,2,3",
927 "CounterHTOff": "0,1,2,3,4,5,6,7"
930 "EventCode": "0xA3",
931 "UMask": "0x8",
941 "EventCode": "0xA3",
942 "UMask": "0x8",
951 "EventCode": "0xA3",
952 "UMask": "0xc",
962 "EventCode": "0xA3",
963 "UMask": "0xc",
972 "EventCode": "0xA8",
973 "UMask": "0x1",
975 "Counter": "0,1,2,3",
978 "CounterHTOff": "0,1,2,3,4,5,6,7"
981 "EventCode": "0xA8",
982 "UMask": "0x1",
984 "Counter": "0,1,2,3",
988 "CounterHTOff": "0,1,2,3,4,5,6,7"
991 "EventCode": "0xA8",
992 "UMask": "0x1",
994 "Counter": "0,1,2,3",
998 "CounterHTOff": "0,1,2,3,4,5,6,7"
1001 "EventCode": "0xB1",
1002 "UMask": "0x1",
1003 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1004 "Counter": "0,1,2,3",
1006 "PublicDescription": "Number of uops to be executed per-thread each cycle.",
1008 "CounterHTOff": "0,1,2,3,4,5,6,7"
1012 "EventCode": "0xB1",
1013 "UMask": "0x1",
1015 "Counter": "0,1,2,3",
1020 "CounterHTOff": "0,1,2,3"
1023 "EventCode": "0xB1",
1024 "UMask": "0x1",
1025 "BriefDescription": "Cycles where at least 1 uop was executed per-thread.",
1026 "Counter": "0,1,2,3",
1030 "CounterHTOff": "0,1,2,3"
1033 "EventCode": "0xB1",
1034 "UMask": "0x1",
1035 "BriefDescription": "Cycles where at least 2 uops were executed per-thread.",
1036 "Counter": "0,1,2,3",
1040 "CounterHTOff": "0,1,2,3"
1043 "EventCode": "0xB1",
1044 "UMask": "0x1",
1045 "BriefDescription": "Cycles where at least 3 uops were executed per-thread.",
1046 "Counter": "0,1,2,3",
1048 "CounterMask": "3",
1050 "CounterHTOff": "0,1,2,3"
1053 "EventCode": "0xB1",
1054 "UMask": "0x1",
1055 "BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
1056 "Counter": "0,1,2,3",
1060 "CounterHTOff": "0,1,2,3"
1063 "EventCode": "0xB1",
1064 "UMask": "0x2",
1066 "Counter": "0,1,2,3",
1070 "CounterHTOff": "0,1,2,3,4,5,6,7"
1073 "EventCode": "0xb1",
1074 "UMask": "0x2",
1075 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1076 "Counter": "0,1,2,3",
1080 "CounterHTOff": "0,1,2,3,4,5,6,7"
1083 "EventCode": "0xb1",
1084 "UMask": "0x2",
1085 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1086 "Counter": "0,1,2,3",
1090 "CounterHTOff": "0,1,2,3,4,5,6,7"
1093 "EventCode": "0xb1",
1094 "UMask": "0x2",
1095 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1096 "Counter": "0,1,2,3",
1098 "CounterMask": "3",
1100 "CounterHTOff": "0,1,2,3,4,5,6,7"
1103 "EventCode": "0xb1",
1104 "UMask": "0x2",
1105 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1106 "Counter": "0,1,2,3",
1110 "CounterHTOff": "0,1,2,3,4,5,6,7"
1114 "EventCode": "0xb1",
1115 "UMask": "0x2",
1116 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1117 "Counter": "0,1,2,3",
1120 "CounterHTOff": "0,1,2,3,4,5,6,7"
1123 "EventCode": "0xC0",
1124 "UMask": "0x0",
1125 … "BriefDescription": "Number of instructions retired. General Counter - architectural event",
1126 "Counter": "0,1,2,3",
1129 …vent counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions in…
1131 "CounterHTOff": "0,1,2,3,4,5,6,7"
1134 "EventCode": "0xC0",
1135 "UMask": "0x1",
1146 "EventCode": "0xC0",
1147 "UMask": "0x2",
1149 "Counter": "0,1,2,3",
1153 "CounterHTOff": "0,1,2,3,4,5,6,7"
1156 "EventCode": "0xC1",
1157 "UMask": "0x40",
1159 "Counter": "0,1,2,3",
1162 "CounterHTOff": "0,1,2,3,4,5,6,7"
1165 "EventCode": "0xC2",
1166 "UMask": "0x1",
1170 "Counter": "0,1,2,3",
1172 …actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused…
1174 "CounterHTOff": "0,1,2,3,4,5,6,7"
1178 "EventCode": "0xC2",
1179 "UMask": "0x1",
1181 "Counter": "0,1,2,3",
1186 "CounterHTOff": "0,1,2,3"
1190 "EventCode": "0xC2",
1191 "UMask": "0x1",
1193 "Counter": "0,1,2,3",
1198 "CounterHTOff": "0,1,2,3"
1201 "EventCode": "0xC2",
1202 "UMask": "0x2",
1205 "Counter": "0,1,2,3",
1209 "CounterHTOff": "0,1,2,3,4,5,6,7"
1212 "EventCode": "0xC3",
1213 "UMask": "0x1",
1214 …"BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nuke…
1215 "Counter": "0,1,2,3",
1217 … "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.",
1219 "CounterHTOff": "0,1,2,3,4,5,6,7"
1223 "EventCode": "0xC3",
1224 "UMask": "0x1",
1226 "Counter": "0,1,2,3",
1230 "CounterHTOff": "0,1,2,3,4,5,6,7"
1233 "EventCode": "0xC3",
1234 "UMask": "0x4",
1235 "BriefDescription": "Self-modifying code (SMC) detected.",
1236 "Counter": "0,1,2,3",
1238 …"PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine…
1240 "CounterHTOff": "0,1,2,3,4,5,6,7"
1243 "EventCode": "0xC3",
1244 "UMask": "0x20",
1245 …el AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
1246 "Counter": "0,1,2,3",
1248 …ription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to in…
1250 "CounterHTOff": "0,1,2,3,4,5,6,7"
1253 "EventCode": "0xC4",
1254 "UMask": "0x0",
1256 "Counter": "0,1,2,3",
1260 "CounterHTOff": "0,1,2,3,4,5,6,7"
1263 "EventCode": "0xC4",
1264 "UMask": "0x1",
1267 "Counter": "0,1,2,3",
1271 "CounterHTOff": "0,1,2,3,4,5,6,7"
1274 "EventCode": "0xC4",
1275 "UMask": "0x2",
1278 "Counter": "0,1,2,3",
1282 "CounterHTOff": "0,1,2,3,4,5,6,7"
1285 "EventCode": "0xC4",
1286 "UMask": "0x2",
1287 …riefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
1289 "Counter": "0,1,2,3",
1291 … event counts both direct and indirect macro near call instructions retired (captured in ring 3).",
1293 "CounterHTOff": "0,1,2,3,4,5,6,7"
1296 "EventCode": "0xC4",
1297 "UMask": "0x4",
1298 "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",
1300 "Counter": "0,1,2,3",
1305 "CounterHTOff": "0,1,2,3"
1308 "EventCode": "0xC4",
1309 "UMask": "0x8",
1312 "Counter": "0,1,2,3",
1316 "CounterHTOff": "0,1,2,3,4,5,6,7"
1319 "EventCode": "0xC4",
1320 "UMask": "0x10",
1322 "Counter": "0,1,2,3",
1326 "CounterHTOff": "0,1,2,3,4,5,6,7"
1329 "EventCode": "0xC4",
1330 "UMask": "0x20",
1333 "Counter": "0,1,2,3",
1337 "CounterHTOff": "0,1,2,3,4,5,6,7"
1340 "EventCode": "0xC4",
1341 "UMask": "0x40",
1343 "Counter": "0,1,2,3",
1348 "CounterHTOff": "0,1,2,3,4,5,6,7"
1351 "EventCode": "0xC5",
1352 "UMask": "0x0",
1354 "Counter": "0,1,2,3",
1358 "CounterHTOff": "0,1,2,3,4,5,6,7"
1361 "EventCode": "0xC5",
1362 "UMask": "0x1",
1365 "Counter": "0,1,2,3",
1369 "CounterHTOff": "0,1,2,3,4,5,6,7"
1372 "EventCode": "0xC5",
1373 "UMask": "0x4",
1374 … "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
1376 "Counter": "0,1,2,3",
1380 "CounterHTOff": "0,1,2,3"
1383 "EventCode": "0xC5",
1384 "UMask": "0x8",
1387 "Counter": "0,1,2,3",
1391 "CounterHTOff": "0,1,2,3,4,5,6,7"
1394 "EventCode": "0xC5",
1395 "UMask": "0x20",
1398 "Counter": "0,1,2,3",
1402 "CounterHTOff": "0,1,2,3,4,5,6,7"
1405 "EventCode": "0xCC",
1406 "UMask": "0x20",
1408 "Counter": "0,1,2,3",
1412 "CounterHTOff": "0,1,2,3,4,5,6,7"
1415 "EventCode": "0xe6",
1416 "UMask": "0x1f",
1418 "Counter": "0,1,2,3",
1421 "CounterHTOff": "0,1,2,3,4,5,6,7"