Lines Matching +full:0 +full:- +full:3
3 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
4 "Counter": "Fixed counter 0",
5 "UMask": "0x1",
9 "CounterHTOff": "Fixed counter 0"
14 "UMask": "0x2",
22 "UMask": "0x2",
32 "UMask": "0x3",
39 …-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store…
40 "EventCode": "0x03",
41 "Counter": "0,1,2,3",
42 "UMask": "0x2",
45 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
46 "CounterHTOff": "0,1,2,3,4,5,6,7"
49 "EventCode": "0x03",
50 "Counter": "0,1,2,3",
51 "UMask": "0x8",
55 "CounterHTOff": "0,1,2,3,4,5,6,7"
59 "EventCode": "0x07",
60 "Counter": "0,1,2,3",
61 "UMask": "0x1",
65 "CounterHTOff": "0,1,2,3,4,5,6,7"
69 "EventCode": "0x0D",
70 "Counter": "0,1,2,3",
71 "UMask": "0x3",
76 "CounterHTOff": "0,1,2,3,4,5,6,7"
79 "EventCode": "0x0D",
80 "Counter": "0,1,2,3",
81 "UMask": "0x3",
87 "CounterHTOff": "0,1,2,3,4,5,6,7"
91 "EventCode": "0x0D",
92 "Counter": "0,1,2,3",
93 "UMask": "0x8",
97 "CounterHTOff": "0,1,2,3,4,5,6,7"
101 "EventCode": "0x0E",
102 "Counter": "0,1,2,3",
103 "UMask": "0x1",
107 "CounterHTOff": "0,1,2,3,4,5,6,7"
111 "EventCode": "0x0E",
113 "Counter": "0,1,2,3",
114 "UMask": "0x1",
119 "CounterHTOff": "0,1,2,3"
122 …ublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitiv…
123 "EventCode": "0x0E",
124 "Counter": "0,1,2,3",
125 "UMask": "0x10",
128 …"BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensiti…
129 "CounterHTOff": "0,1,2,3,4,5,6,7"
132 "EventCode": "0x0E",
133 "Counter": "0,1,2,3",
134 "UMask": "0x20",
137 …w LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sour…
138 "CounterHTOff": "0,1,2,3,4,5,6,7"
141 "EventCode": "0x0E",
142 "Counter": "0,1,2,3",
143 "UMask": "0x40",
147 "CounterHTOff": "0,1,2,3,4,5,6,7"
150 …: "This event counts the number of the divide operations executed. Uses edge-detect and a cmask va…
151 "EventCode": "0x14",
152 "Counter": "0,1,2,3",
153 "UMask": "0x1",
157 "CounterHTOff": "0,1,2,3,4,5,6,7"
161 "EventCode": "0x3C",
162 "Counter": "0,1,2,3",
163 "UMask": "0x0",
167 "CounterHTOff": "0,1,2,3,4,5,6,7"
170 "EventCode": "0x3C",
171 "Counter": "0,1,2,3",
172 "UMask": "0x0",
177 "CounterHTOff": "0,1,2,3,4,5,6,7"
180 …"PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts wh…
181 "EventCode": "0x3C",
182 "Counter": "0,1,2,3",
183 "UMask": "0x1",
187 "CounterHTOff": "0,1,2,3,4,5,6,7"
190 "EventCode": "0x3C",
191 "Counter": "0,1,2,3",
192 "UMask": "0x1",
197 "CounterHTOff": "0,1,2,3,4,5,6,7"
201 "EventCode": "0x3C",
202 "Counter": "0,1,2,3",
203 "UMask": "0x1",
207 "CounterHTOff": "0,1,2,3,4,5,6,7"
210 "EventCode": "0x3C",
211 "Counter": "0,1,2,3",
212 "UMask": "0x1",
217 "CounterHTOff": "0,1,2,3,4,5,6,7"
220 "EventCode": "0x3c",
221 "Counter": "0,1,2,3",
222 "UMask": "0x2",
226 "CounterHTOff": "0,1,2,3"
229 "EventCode": "0x3C",
230 "Counter": "0,1,2,3",
231 "UMask": "0x2",
235 "CounterHTOff": "0,1,2,3,4,5,6,7"
238 …"PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fil…
239 "EventCode": "0x4c",
240 "Counter": "0,1,2,3",
241 "UMask": "0x1",
244 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
245 "CounterHTOff": "0,1,2,3,4,5,6,7"
248 …"PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fil…
249 "EventCode": "0x4C",
250 "Counter": "0,1,2,3",
251 "UMask": "0x2",
254 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
255 "CounterHTOff": "0,1,2,3,4,5,6,7"
258 "EventCode": "0x58",
259 "Counter": "0,1,2,3",
260 "UMask": "0x1",
264 "CounterHTOff": "0,1,2,3,4,5,6,7"
267 "EventCode": "0x58",
268 "Counter": "0,1,2,3",
269 "UMask": "0x2",
273 "CounterHTOff": "0,1,2,3,4,5,6,7"
276 "EventCode": "0x58",
277 "Counter": "0,1,2,3",
278 "UMask": "0x4",
282 "CounterHTOff": "0,1,2,3,4,5,6,7"
285 "EventCode": "0x58",
286 "Counter": "0,1,2,3",
287 "UMask": "0x8",
291 "CounterHTOff": "0,1,2,3,4,5,6,7"
294 …vation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. …
295 "EventCode": "0x5E",
296 "Counter": "0,1,2,3",
297 "UMask": "0x1",
301 "CounterHTOff": "0,1,2,3,4,5,6,7"
304 "EventCode": "0x5E",
306 "Counter": "0,1,2,3",
307 "UMask": "0x1",
313 "CounterHTOff": "0,1,2,3,4,5,6,7"
316 …he number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penal…
317 "EventCode": "0x87",
318 "Counter": "0,1,2,3",
319 "UMask": "0x1",
323 "CounterHTOff": "0,1,2,3,4,5,6,7"
326 "PublicDescription": "This event counts not taken macro-conditional branch instructions.",
327 "EventCode": "0x88",
328 "Counter": "0,1,2,3",
329 "UMask": "0x41",
332 "BriefDescription": "Not taken macro-conditional branches",
333 "CounterHTOff": "0,1,2,3,4,5,6,7"
336 …"PublicDescription": "This event counts taken speculative and retired macro-conditional branch ins…
337 "EventCode": "0x88",
338 "Counter": "0,1,2,3",
339 "UMask": "0x81",
342 "BriefDescription": "Taken speculative and retired macro-conditional branches",
343 "CounterHTOff": "0,1,2,3,4,5,6,7"
346 …"PublicDescription": "This event counts taken speculative and retired macro-conditional branch ins…
347 "EventCode": "0x88",
348 "Counter": "0,1,2,3",
349 "UMask": "0x82",
352 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
353 "CounterHTOff": "0,1,2,3,4,5,6,7"
357 "EventCode": "0x88",
358 "Counter": "0,1,2,3",
359 "UMask": "0x84",
363 "CounterHTOff": "0,1,2,3,4,5,6,7"
367 "EventCode": "0x88",
368 "Counter": "0,1,2,3",
369 "UMask": "0x88",
373 "CounterHTOff": "0,1,2,3,4,5,6,7"
377 "EventCode": "0x88",
378 "Counter": "0,1,2,3",
379 "UMask": "0x90",
383 "CounterHTOff": "0,1,2,3,4,5,6,7"
387 "EventCode": "0x88",
388 "Counter": "0,1,2,3",
389 "UMask": "0xa0",
393 "CounterHTOff": "0,1,2,3,4,5,6,7"
396 …": "This event counts both taken and not taken speculative and retired macro-conditional branch in…
397 "EventCode": "0x88",
398 "Counter": "0,1,2,3",
399 "UMask": "0xc1",
402 "BriefDescription": "Speculative and retired macro-conditional branches",
403 "CounterHTOff": "0,1,2,3,4,5,6,7"
406 …": "This event counts both taken and not taken speculative and retired macro-unconditional branch …
407 "EventCode": "0x88",
408 "Counter": "0,1,2,3",
409 "UMask": "0xc2",
412 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
413 "CounterHTOff": "0,1,2,3,4,5,6,7"
417 "EventCode": "0x88",
418 "Counter": "0,1,2,3",
419 "UMask": "0xc4",
423 "CounterHTOff": "0,1,2,3,4,5,6,7"
427 "EventCode": "0x88",
428 "Counter": "0,1,2,3",
429 "UMask": "0xc8",
433 "CounterHTOff": "0,1,2,3,4,5,6,7"
437 "EventCode": "0x88",
438 "Counter": "0,1,2,3",
439 "UMask": "0xd0",
443 "CounterHTOff": "0,1,2,3,4,5,6,7"
447 "EventCode": "0x88",
448 "Counter": "0,1,2,3",
449 "UMask": "0xff",
453 "CounterHTOff": "0,1,2,3,4,5,6,7"
457 "EventCode": "0x89",
458 "Counter": "0,1,2,3",
459 "UMask": "0x41",
463 "CounterHTOff": "0,1,2,3,4,5,6,7"
467 "EventCode": "0x89",
468 "Counter": "0,1,2,3",
469 "UMask": "0x81",
473 "CounterHTOff": "0,1,2,3,4,5,6,7"
477 "EventCode": "0x89",
478 "Counter": "0,1,2,3",
479 "UMask": "0x84",
483 "CounterHTOff": "0,1,2,3,4,5,6,7"
487 "EventCode": "0x89",
488 "Counter": "0,1,2,3",
489 "UMask": "0x88",
493 "CounterHTOff": "0,1,2,3,4,5,6,7"
496 "EventCode": "0x89",
497 "Counter": "0,1,2,3",
498 "UMask": "0xa0",
502 "CounterHTOff": "0,1,2,3,4,5,6,7"
506 "EventCode": "0x89",
507 "Counter": "0,1,2,3",
508 "UMask": "0xc1",
512 "CounterHTOff": "0,1,2,3,4,5,6,7"
516 "EventCode": "0x89",
517 "Counter": "0,1,2,3",
518 "UMask": "0xc4",
522 "CounterHTOff": "0,1,2,3,4,5,6,7"
526 "EventCode": "0x89",
527 "Counter": "0,1,2,3",
528 "UMask": "0xff",
532 "CounterHTOff": "0,1,2,3,4,5,6,7"
535 …"PublicDescription": "This event counts the number of micro-operations cancelled after they were d…
536 "EventCode": "0xA0",
537 "Counter": "0,1,2,3",
538 "UMask": "0x3",
541 …"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file…
542 "CounterHTOff": "0,1,2,3"
545 …is event counts, on the per-thread basis, cycles during which uops are dispatched from the Reserva…
546 "EventCode": "0xA1",
547 "Counter": "0,1,2,3",
548 "UMask": "0x1",
551 "BriefDescription": "Cycles per thread when uops are executed in port 0",
552 "CounterHTOff": "0,1,2,3,4,5,6,7"
555 "EventCode": "0xA1",
556 "Counter": "0,1,2,3",
557 "UMask": "0x1",
561 "BriefDescription": "Cycles per core when uops are exectuted in port 0.",
562 "CounterHTOff": "0,1,2,3,4,5,6,7"
565 …is event counts, on the per-thread basis, cycles during which uops are dispatched from the Reserva…
566 "EventCode": "0xA1",
567 "Counter": "0,1,2,3",
568 "UMask": "0x1",
571 "BriefDescription": "Cycles per thread when uops are executed in port 0",
572 "CounterHTOff": "0,1,2,3,4,5,6,7"
575 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
576 "EventCode": "0xA1",
577 "Counter": "0,1,2,3",
578 "UMask": "0x2",
582 "CounterHTOff": "0,1,2,3,4,5,6,7"
585 "EventCode": "0xA1",
586 "Counter": "0,1,2,3",
587 "UMask": "0x2",
592 "CounterHTOff": "0,1,2,3,4,5,6,7"
595 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
596 "EventCode": "0xA1",
597 "Counter": "0,1,2,3",
598 "UMask": "0x2",
602 "CounterHTOff": "0,1,2,3,4,5,6,7"
605 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
606 "EventCode": "0xA1",
607 "Counter": "0,1,2,3",
608 "UMask": "0x4",
612 "CounterHTOff": "0,1,2,3,4,5,6,7"
615 "EventCode": "0xA1",
616 "Counter": "0,1,2,3",
617 "UMask": "0x4",
622 "CounterHTOff": "0,1,2,3,4,5,6,7"
625 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
626 "EventCode": "0xA1",
627 "Counter": "0,1,2,3",
628 "UMask": "0x4",
632 "CounterHTOff": "0,1,2,3,4,5,6,7"
635 …is event counts, on the per-thread basis, cycles during which uops are dispatched from the Reserva…
636 "EventCode": "0xA1",
637 "Counter": "0,1,2,3",
638 "UMask": "0x8",
641 "BriefDescription": "Cycles per thread when uops are executed in port 3",
642 "CounterHTOff": "0,1,2,3,4,5,6,7"
645 "EventCode": "0xA1",
646 "Counter": "0,1,2,3",
647 "UMask": "0x8",
651 "BriefDescription": "Cycles per core when uops are dispatched to port 3.",
652 "CounterHTOff": "0,1,2,3,4,5,6,7"
655 …is event counts, on the per-thread basis, cycles during which uops are dispatched from the Reserva…
656 "EventCode": "0xA1",
657 "Counter": "0,1,2,3",
658 "UMask": "0x8",
661 "BriefDescription": "Cycles per thread when uops are executed in port 3",
662 "CounterHTOff": "0,1,2,3,4,5,6,7"
665 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
666 "EventCode": "0xA1",
667 "Counter": "0,1,2,3",
668 "UMask": "0x10",
672 "CounterHTOff": "0,1,2,3,4,5,6,7"
675 "EventCode": "0xA1",
676 "Counter": "0,1,2,3",
677 "UMask": "0x10",
682 "CounterHTOff": "0,1,2,3,4,5,6,7"
685 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
686 "EventCode": "0xA1",
687 "Counter": "0,1,2,3",
688 "UMask": "0x10",
692 "CounterHTOff": "0,1,2,3,4,5,6,7"
695 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
696 "EventCode": "0xA1",
697 "Counter": "0,1,2,3",
698 "UMask": "0x20",
702 "CounterHTOff": "0,1,2,3,4,5,6,7"
705 "EventCode": "0xA1",
706 "Counter": "0,1,2,3",
707 "UMask": "0x20",
712 "CounterHTOff": "0,1,2,3,4,5,6,7"
715 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
716 "EventCode": "0xA1",
717 "Counter": "0,1,2,3",
718 "UMask": "0x20",
722 "CounterHTOff": "0,1,2,3,4,5,6,7"
725 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
726 "EventCode": "0xA1",
727 "Counter": "0,1,2,3",
728 "UMask": "0x40",
732 "CounterHTOff": "0,1,2,3,4,5,6,7"
735 "EventCode": "0xA1",
736 "Counter": "0,1,2,3",
737 "UMask": "0x40",
742 "CounterHTOff": "0,1,2,3,4,5,6,7"
745 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
746 "EventCode": "0xA1",
747 "Counter": "0,1,2,3",
748 "UMask": "0x40",
752 "CounterHTOff": "0,1,2,3,4,5,6,7"
755 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
756 "EventCode": "0xA1",
757 "Counter": "0,1,2,3",
758 "UMask": "0x80",
762 "CounterHTOff": "0,1,2,3,4,5,6,7"
765 "EventCode": "0xA1",
766 "Counter": "0,1,2,3",
767 "UMask": "0x80",
772 "CounterHTOff": "0,1,2,3,4,5,6,7"
775 …"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dis…
776 "EventCode": "0xA1",
777 "Counter": "0,1,2,3",
778 "UMask": "0x80",
782 "CounterHTOff": "0,1,2,3,4,5,6,7"
785 "PublicDescription": "This event counts resource-related stall cycles.",
786 "EventCode": "0xa2",
787 "Counter": "0,1,2,3",
788 "UMask": "0x1",
791 "BriefDescription": "Resource-related stall cycles",
792 "CounterHTOff": "0,1,2,3,4,5,6,7"
796 "EventCode": "0xA2",
797 "Counter": "0,1,2,3",
798 "UMask": "0x4",
802 "CounterHTOff": "0,1,2,3,4,5,6,7"
806 "EventCode": "0xA2",
807 "Counter": "0,1,2,3",
808 "UMask": "0x8",
812 "CounterHTOff": "0,1,2,3,4,5,6,7"
816 "EventCode": "0xA2",
817 "Counter": "0,1,2,3",
818 "UMask": "0x10",
821 "BriefDescription": "Cycles stalled due to re-order buffer full.",
822 "CounterHTOff": "0,1,2,3,4,5,6,7"
826 "EventCode": "0xA3",
827 "Counter": "0,1,2,3",
828 "UMask": "0x1",
833 "CounterHTOff": "0,1,2,3,4,5,6,7"
836 "EventCode": "0xA3",
837 "Counter": "0,1,2,3",
838 "UMask": "0x1",
843 "CounterHTOff": "0,1,2,3,4,5,6,7"
846 …e CPU has at least one pending demand load request (that is cycles with non-completed load waitin…
847 "EventCode": "0xA3",
848 "Counter": "0,1,2,3",
849 "UMask": "0x2",
854 "CounterHTOff": "0,1,2,3,4,5,6,7"
857 "EventCode": "0xA3",
858 "Counter": "0,1,2,3",
859 "UMask": "0x2",
864 "CounterHTOff": "0,1,2,3"
868 "EventCode": "0xA3",
869 "Counter": "0,1,2,3",
870 "UMask": "0x4",
875 "CounterHTOff": "0,1,2,3"
878 "EventCode": "0xA3",
879 "Counter": "0,1,2,3",
880 "UMask": "0x4",
885 "CounterHTOff": "0,1,2,3,4,5,6,7"
889 "EventCode": "0xA3",
890 "Counter": "0,1,2,3",
891 "UMask": "0x5",
896 "CounterHTOff": "0,1,2,3"
899 "EventCode": "0xA3",
900 "Counter": "0,1,2,3",
901 "UMask": "0x5",
906 "CounterHTOff": "0,1,2,3,4,5,6,7"
910 "EventCode": "0xA3",
911 "Counter": "0,1,2,3",
912 "UMask": "0x6",
917 "CounterHTOff": "0,1,2,3"
920 "EventCode": "0xA3",
921 "Counter": "0,1,2,3",
922 "UMask": "0x6",
927 "CounterHTOff": "0,1,2,3,4,5,6,7"
931 "EventCode": "0xA3",
933 "UMask": "0x8",
941 "EventCode": "0xA3",
943 "UMask": "0x8",
952 "EventCode": "0xA3",
954 "UMask": "0xc",
962 "EventCode": "0xA3",
964 "UMask": "0xc",
973 "EventCode": "0xA8",
974 "Counter": "0,1,2,3",
975 "UMask": "0x1",
979 "CounterHTOff": "0,1,2,3,4,5,6,7"
982 "EventCode": "0xA8",
983 "Counter": "0,1,2,3",
984 "UMask": "0x1",
989 "CounterHTOff": "0,1,2,3,4,5,6,7"
992 "EventCode": "0xA8",
993 "Counter": "0,1,2,3",
994 "UMask": "0x1",
999 "CounterHTOff": "0,1,2,3,4,5,6,7"
1002 "PublicDescription": "Number of uops to be executed per-thread each cycle.",
1003 "EventCode": "0xB1",
1004 "Counter": "0,1,2,3",
1005 "UMask": "0x1",
1008 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1009 "CounterHTOff": "0,1,2,3,4,5,6,7"
1013 "EventCode": "0xB1",
1015 "Counter": "0,1,2,3",
1016 "UMask": "0x1",
1021 "CounterHTOff": "0,1,2,3"
1024 "EventCode": "0xB1",
1025 "Counter": "0,1,2,3",
1026 "UMask": "0x1",
1029 "BriefDescription": "Cycles where at least 1 uop was executed per-thread.",
1031 "CounterHTOff": "0,1,2,3"
1034 "EventCode": "0xB1",
1035 "Counter": "0,1,2,3",
1036 "UMask": "0x1",
1039 "BriefDescription": "Cycles where at least 2 uops were executed per-thread.",
1041 "CounterHTOff": "0,1,2,3"
1044 "EventCode": "0xB1",
1045 "Counter": "0,1,2,3",
1046 "UMask": "0x1",
1049 "BriefDescription": "Cycles where at least 3 uops were executed per-thread.",
1050 "CounterMask": "3",
1051 "CounterHTOff": "0,1,2,3"
1054 "EventCode": "0xB1",
1055 "Counter": "0,1,2,3",
1056 "UMask": "0x1",
1059 "BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
1061 "CounterHTOff": "0,1,2,3"
1065 "EventCode": "0xB1",
1066 "Counter": "0,1,2,3",
1067 "UMask": "0x2",
1071 "CounterHTOff": "0,1,2,3,4,5,6,7"
1074 "EventCode": "0xb1",
1075 "Counter": "0,1,2,3",
1076 "UMask": "0x2",
1079 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1081 "CounterHTOff": "0,1,2,3,4,5,6,7"
1084 "EventCode": "0xb1",
1085 "Counter": "0,1,2,3",
1086 "UMask": "0x2",
1089 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1091 "CounterHTOff": "0,1,2,3,4,5,6,7"
1094 "EventCode": "0xb1",
1095 "Counter": "0,1,2,3",
1096 "UMask": "0x2",
1099 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1100 "CounterMask": "3",
1101 "CounterHTOff": "0,1,2,3,4,5,6,7"
1104 "EventCode": "0xb1",
1105 "Counter": "0,1,2,3",
1106 "UMask": "0x2",
1109 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1111 "CounterHTOff": "0,1,2,3,4,5,6,7"
1114 "EventCode": "0xb1",
1116 "Counter": "0,1,2,3",
1117 "UMask": "0x2",
1120 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1121 "CounterHTOff": "0,1,2,3,4,5,6,7"
1124 …vent counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions in…
1125 "EventCode": "0xC0",
1126 "Counter": "0,1,2,3",
1127 "UMask": "0x0",
1131 … "BriefDescription": "Number of instructions retired. General Counter - architectural event",
1132 "CounterHTOff": "0,1,2,3,4,5,6,7"
1137 "EventCode": "0xC0",
1139 "UMask": "0x1",
1149 "EventCode": "0xC0",
1150 "Counter": "0,1,2,3",
1151 "UMask": "0x2",
1155 "CounterHTOff": "0,1,2,3,4,5,6,7"
1159 "EventCode": "0xC1",
1160 "Counter": "0,1,2,3",
1161 "UMask": "0x40",
1164 "CounterHTOff": "0,1,2,3,4,5,6,7"
1168 …actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused…
1169 "EventCode": "0xC2",
1170 "Counter": "0,1,2,3",
1171 "UMask": "0x1",
1174 "BriefDescription": "Actually retired uops. (Precise Event - PEBS)",
1175 "CounterHTOff": "0,1,2,3,4,5,6,7",
1181 "EventCode": "0xC2",
1183 "Counter": "0,1,2,3",
1184 "UMask": "0x1",
1189 "CounterHTOff": "0,1,2,3"
1194 "EventCode": "0xC2",
1196 "Counter": "0,1,2,3",
1197 "UMask": "0x1",
1202 "CounterHTOff": "0,1,2,3"
1207 "EventCode": "0xC2",
1208 "Counter": "0,1,2,3",
1209 "UMask": "0x2",
1212 "BriefDescription": "Retirement slots used. (Precise Event - PEBS)",
1213 "CounterHTOff": "0,1,2,3,4,5,6,7"
1216 … "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.",
1217 "EventCode": "0xC3",
1218 "Counter": "0,1,2,3",
1219 "UMask": "0x1",
1222 …"BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nuke…
1223 "CounterHTOff": "0,1,2,3,4,5,6,7"
1226 "EventCode": "0xC3",
1227 "Counter": "0,1,2,3",
1228 "UMask": "0x1",
1234 "CounterHTOff": "0,1,2,3,4,5,6,7"
1237 …"PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine…
1238 "EventCode": "0xC3",
1239 "Counter": "0,1,2,3",
1240 "UMask": "0x4",
1243 "BriefDescription": "Self-modifying code (SMC) detected.",
1244 "CounterHTOff": "0,1,2,3,4,5,6,7"
1247 …ription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to in…
1248 "EventCode": "0xC3",
1249 "Counter": "0,1,2,3",
1250 "UMask": "0x20",
1253 …el AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
1254 "CounterHTOff": "0,1,2,3,4,5,6,7"
1258 "EventCode": "0xC4",
1259 "Counter": "0,1,2,3",
1260 "UMask": "0x0",
1264 "CounterHTOff": "0,1,2,3,4,5,6,7"
1269 "EventCode": "0xC4",
1270 "Counter": "0,1,2,3",
1271 "UMask": "0x1",
1274 "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS)",
1275 "CounterHTOff": "0,1,2,3,4,5,6,7"
1280 "EventCode": "0xC4",
1281 "Counter": "0,1,2,3",
1282 "UMask": "0x2",
1285 … "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS)",
1286 "CounterHTOff": "0,1,2,3,4,5,6,7"
1290 …t that counts both direct and indirect macro near call instructions retired (captured in ring 3).",
1291 "EventCode": "0xC4",
1292 "Counter": "0,1,2,3",
1293 "UMask": "0x2",
1296 …ct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS)",
1297 "CounterHTOff": "0,1,2,3,4,5,6,7"
1302 "EventCode": "0xC4",
1303 "Counter": "0,1,2,3",
1304 "UMask": "0x4",
1308 "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",
1309 "CounterHTOff": "0,1,2,3"
1314 "EventCode": "0xC4",
1315 "Counter": "0,1,2,3",
1316 "UMask": "0x8",
1319 "BriefDescription": "Return instructions retired. (Precise Event - PEBS)",
1320 "CounterHTOff": "0,1,2,3,4,5,6,7"
1325 "EventCode": "0xC4",
1326 "Counter": "0,1,2,3",
1327 "UMask": "0x10",
1331 "CounterHTOff": "0,1,2,3,4,5,6,7"
1336 "EventCode": "0xC4",
1337 "Counter": "0,1,2,3",
1338 "UMask": "0x20",
1341 "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS)",
1342 "CounterHTOff": "0,1,2,3,4,5,6,7"
1347 "EventCode": "0xC4",
1348 "Counter": "0,1,2,3",
1349 "UMask": "0x40",
1354 "CounterHTOff": "0,1,2,3,4,5,6,7"
1358 "EventCode": "0xC5",
1359 "Counter": "0,1,2,3",
1360 "UMask": "0x0",
1364 "CounterHTOff": "0,1,2,3,4,5,6,7"
1369 "EventCode": "0xC5",
1370 "Counter": "0,1,2,3",
1371 "UMask": "0x1",
1374 …"BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS)",
1375 "CounterHTOff": "0,1,2,3,4,5,6,7"
1380 "EventCode": "0xC5",
1381 "Counter": "0,1,2,3",
1382 "UMask": "0x4",
1385 … "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
1386 "CounterHTOff": "0,1,2,3"
1391 "EventCode": "0xC5",
1392 "Counter": "0,1,2,3",
1393 "UMask": "0x8",
1397 "CounterHTOff": "0,1,2,3,4,5,6,7"
1401 …ber of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).",
1402 "EventCode": "0xC5",
1403 "Counter": "0,1,2,3",
1404 "UMask": "0x20",
1407 …ber of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).",
1408 "CounterHTOff": "0,1,2,3,4,5,6,7"
1412 "EventCode": "0xCC",
1413 "Counter": "0,1,2,3",
1414 "UMask": "0x20",
1418 "CounterHTOff": "0,1,2,3,4,5,6,7"
1421 "EventCode": "0xe6",
1422 "Counter": "0,1,2,3",
1423 "UMask": "0x1f",
1427 "CounterHTOff": "0,1,2,3,4,5,6,7"