Lines Matching full:including

46 …: "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches…
52 …: "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
206 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
212 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
218 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
224 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
230 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
236 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
242 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
248 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
254 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
260 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
266 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…