Lines Matching full:side
50 …dified (M) data from another core's ECO L3 on the same chip due to a data side request. When using…
455 "BriefDescription": "D-side L2 MRU touch commands sent to the L2"
510 …red (S) data from another core's L2 on the same chip due to a marked data side request. When using…
660 …"BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread t…
705 …"BriefDescription": "All successful D-side-Ld/St or I-side-instruction-fetch dispatches for this t…
825 …"BriefDescription": "All successful D-side-Ld or I-side-instruction-fetch dispatches for this thre…
845 …"BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread t…
1055 …nother core's L2/L3 on a different chip (remote or distant) due to a data side request. When using…
1125 …ble Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request"
1160 …"BriefDescription": "All I-side-instruction-fetch dispatch attempts for this thread that failed du…
1225 …"BriefDescription": "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for…
1250 …"BriefDescription": "Valid when first beat of data comes in for an D-side fetch where data came EX…
1275 …"BriefDescription": "Valid when first beat of data comes in for an D-side fetch where data came EX…
1295 …"BriefDescription": "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for…
1300 "BriefDescription": "All successful D-Side Load dispatches that were an L2 miss for this thread"
1320 …Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request"
1370 …"BriefDescription": "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) fo…
1405 "BriefDescription": "All D-side store dispatch attempts for this thread"
1410 …"BriefDescription": "All D-side store dispatch attempts for this thread that failed due to reason …
1430 …"BriefDescription": "All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatche…
1435 …LB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request"
1445 "BriefDescription": "All I-side-instruction-fetch dispatch attempts for this thread"
1500 …"BriefDescription": "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) fo…
1505 …"BriefDescription": "Valid when first beat of data comes in for an I-side fetch where data came fr…
1560 …ry was loaded into the TLB from local core's L2 without conflict due to a instruction side request"
1570 … loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request"
1595 …"BriefDescription": "All successful D-side-Ld or I-side-instruction-fetch dispatches for this thre…
1635 …"BriefDescription": "All I-side-instruction-fetch dispatch attempts for this thread that failed du…
1685 …B from another chip's memory on the same Node or Group (Distant) due to a instruction side request"
1705 …cal core's L2 hit without dispatch conflicts on Mepf state. due to a data side request. When using…
1715 …"BriefDescription": "I-side L2 MRU touch sent to L2 for this thread I-side L2 MRU touch commands s…
1785 "BriefDescription": "All successful D-side store dispatches for this thread that were L2 hits"
1805 … "BriefDescription": "All successful D-Side Store dispatches that were an L2 miss for this thread"
1815 …'s L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request"
1895 … from another chip's L4 on the same Node or Group ( Remote) due to a data side request. When using…
1950 …nother chip's L4 on the same Node or Group ( Remote) due to a marked data side request. When using…
1990 "BriefDescription": "All successful D-side Load dispatches for this thread (L2 miss + L2 hits)"
2010 …red (S) data from another core's L3 on the same chip due to a marked data side request.. When usin…
2035 …into the TLB from a location other than the local core's L2 due to a data side request. When using…
2060 …or modified data from another core's L2/L3 on the same chip due to a data side request. When using…
2095 … "BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread"
2200 "BriefDescription": "All successful D-side store dispatches for this thread"
2205 …"BriefDescription": "All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatche…
2240 "BriefDescription": "All successful D-side store dispatches for this thread (L2 miss + L2 hits)"
2330 …"BriefDescription": "All D-side store dispatch attempts for this thread that failed due to address…